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Circuits, Devices and Systems, IEE Proceedings G

Issue 6 • Date Dec 1993

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Displaying Results 1 - 13 of 13
  • Logic design based on negative differential resistance characteristics of quantum electronic devices

    Page(s): 383 - 391
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    New quantum electronic devices such as resonant tunnelling diodes and transistors have negative differential resistance characteristics that can be exploited to design novel high-speed circuits. The high intrinsic switching speed of these devices, combined with the novel circuit structures used to implement standard logic functions, leads to ultrafast computing circuits. The new circuit structures presented here provide extremely compact implementations of functions such as carry generation and addition. The most significant impact of these circuits on the field of logic design is the introduction of a totally new set of relative costs of various basic gates; re-evaluation of the logic in the light of these new cost functions leads to ultrafast and compact designs View full abstract»

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  • Equivalent circuit for a GaAs CCD

    Page(s): 377 - 382
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    An equivalent circuit model was proposed for the charge transfer mechanisms in a GaAs charge coupled device (CCD). Realistic simulations were carried out to assess the model at different transfer times and for different sizes of the charge packet. A comparison was also made with an analytical model and the results were quite close. Simulations of the input and the output stages of the device were also examined. The key advantages of the equivalent circuit model appeared to be substantial reduction in the computing time in addition to its primary use in a circuit simulator View full abstract»

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  • Log-domain filtering: an approach to current-mode filtering

    Page(s): 406 - 416
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A novel approach to filter design, based on Adams' `log-domain' filters, is proposed that yields a truly current-mode circuit realisation. Adams' idea, which was introduced in a limited context, is generalised to permit a complete distortionless synthesis procedure, which results in circuit implementations readily realisable using complementary bipolar processes. It is shown that, by introducing an exponential map on the state-space description of the desired linear system, a log-domain filter can be fully realised with transistors configured in current mirror-type groupings, current sources and capacitors. Owing to the mapping, the state variables are intrinsically related to current, and not voltage, in the resulting circuits, a fact that emphasises the current-mode nature of the design. A general biquadratic filter section is designed, and, following discussion of cascading sections, a seventh-order Chebychev lowpass filter is designed. All designed circuits are shown to be tunable over a two-decade range in frequency while their characteristics are accurately preserved, even for biquad sections whose f0Q product is greater than fT/10. The Chebychev filter is shown in simulation to possess nearly 60 dB dynamic range relative to 0.9% THD, with a cutoff frequency of nearly 5 MHz, using transistor models from AT&T's CBIC-R 300 Hz complementary bipolar process View full abstract»

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  • Analytically extracted ZTC point for GaAs MESFET

    Page(s): 424 - 430
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Some current-voltage characteristics of GaAs MESFET at elevated temperatures have been measured and the existence of zero temperature coefficient (ZTC) points in the drain current of DFETs and EFETs are presented. At these points of operation, with a specific value of gate bias, the device drain current characteristics are stable in temperature. The ZTC point for the saturation region of operation is presented for both types of devices, whereas for the linear region of operation the ZTC point is reached only with DFET. The existence of the ZTC point is shown to depend critically on the flow of leakage currents. The ZTC points are analysed with an analytical model that is capable of estimating the corresponding drain current and gate bias values. In addition, an analytical model for the threshold voltage and transconductance parameter is discussed by starting from device physical and geometrical parameters for finding the ZTC point. The analytically solved results are shown to correspond closely to the experimental results View full abstract»

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  • Asymptotic stability of equilibrium points in dynamical neural networks

    Page(s): 401 - 405
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    In most applications of feedback neural networks, such as the realisation of associative memories, the asymptotic stability of specific equilibrium points is the main design requirement. Sufficient conditions are presented which simplify the checking that an isolated equilibrium point is asymptotically stable. Then, these conditions are generalised to the characterisation of all equilibrium points in an open region of the state space. Finally, an explicit lower bound on the exponential convergence rate, to an equilibrium, is derived View full abstract»

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  • Digital filters implementation using DPCM video signal processing

    Page(s): 453 - 461
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    A new realisation of DPCM video signal/image processing is introduced to increase the throughput rate and reduce the hardware cost of the 2D systolic digital filters. This achieved by using a DPCM coding system with a 2D predictor and a 27-level symmetric nonuniform quantiser prior to processing. The advantage of the symmetric nonuniform quantiser is that the size of memory required for multiplication is reduced by a factor of 16 compared to 4 in the existing DPCM implementations. It is shown that the new realisation results in a 64% increase in the throughput rate and a significant reduction in the hardware cost. From the objective and subjective tests carried out, it is shown that the new realisation results in images with visual quality similar to those obtained using conventional processing. Also, the effect of the choice of the 2D predictor is discussed, where it is shown that a 2D predictor with integer coefficients is the most appropriate for DPCM processing View full abstract»

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  • Theoretical and experimental results for the inversion channel heterostructure field effect transistor

    Page(s): 392 - 400
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    New theoretical and experimental findings are presented to address the modelling needs of inversion channel optoelectronic integrated circuit (OEICs). This FET is well suited to OEICs since the gate is an ohmic contact controlling the channel conductivity from a substantial distance. Consequently, the region around the channel is formed as a graded index structure with a single or multiple quantum well active region which allows the FET to operate as a laser, a detector and an absorption modulator forming a complete component base for integration. It is shown that the threshold voltage of this FET demonstrates unique dependencies on charge sheet, barrier, and collector dopings, which allows wide design flexibility and a substantially higher operating voltage than other III-V FETS. The effect of device length on threshold is examined experimentally and it is found that the gradient dVTH /dL may be positive or negative which raises the prospect that the condition dVTH/dL≃0 may be found to allow scaling to very small dimensions. The device threshold and the bipolar injection from the gate contact are controlled by a p contact to the collector region which serves as an additional gate for the FET View full abstract»

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  • Capacitance-time transient characteristics of pulsed MOS capacitor application in measurement of semiconductor parameters

    Page(s): 449 - 452
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    Using Rabbani's model for generation width, a differential equation, which describes the capacitance-time (C-t) transient characteristics of pulsed MOS capacitors was obtained. The theoretical (C-t) transient characteristics can be obtained by integrating this differential equation. It has also been shown that the minority generation lifetime of semiconductors can be determined by matching an experimental (C-t) transient characteristic with the theoretical one View full abstract»

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  • Current-mode oscillator realisation using a voltage-to-current transducer in CMOS technology

    Page(s): 462 - 464
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A voltage-to-current transducer implementable in CMOS integrated circuit technology is described. Admittance parameter formulation reveals the potential for implementation of an inductor using the gyrator concept. The inductor is applied to build a current-mode oscillator. Simulation results are provided View full abstract»

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  • New multibit delta-sigma modulator structure with reduced sensitivity to the D/A conversion error

    Page(s): 444 - 448
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A new structure is presented for multibit delta-sigma modulators, where the D/A conversion error as well as the A/D conversion error (the quantisation noise) is spectrally shaped. Thus the requirement on the accuracy of the D/A convertor is relaxed without sacrificing the advantages of using a multibit A/D convertor in delta-sigma modulators. The new structure also has a feature of design flexibility, for the choice of the noise shaping function does not have strong influence on the signal in the passband. Both analysis and simulation show that the new structure is relatively tolerant of analogue component inaccuracies View full abstract»

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  • Class E resonant low di/dt rectifier

    Page(s): 417 - 423
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    An analysis and experimental verification of a Class E voltage-driven resonant low di/dt rectifier are given. The circuit contains two resonant components: an inductor and a capacitor. Design equations are derived using Fourier series techniques. A prototype of the rectifier was built and tested at 500 KHz and an output voltage of 5 V. The theoretical and experimental results were in good agreement. The rectifier offers soft switching of the diode, decreasing noise and switching losses. However, the diode junction capacitance and the resonant components form a detrimental resonant circuit during the diode off state, causing ringing superimposed on the desirable waveforms View full abstract»

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  • Power dissipation models and performance improvement techniques for CMOS inverters with RC line and tree interconnections

    Page(s): 437 - 443
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    Physical power dissipation models of CMOS inverters with RC line and tree interconnection networks are presented. Compared to SPICE simulation results, the maximum error in the model calculated results using the models is 12% for power dissipation in CMOS inverters with different RC values in each branch of the tree networks, different gate sizes, device parameters, and even input excitation waveforms not deviating much from the characteristic waveforms. Based upon the mathematical optimisation method, as well as on the developed power dissipation models and the delay models, an experimental sizing program is also constructed for improving various circuit performances such as delay time, power-delay product, and delay time with fixed power dissipation specifications. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one improvement technique and determine the suitable sizes and/or number of drivers/repeaters for optimal circuit performance. It is found from the sizing results of the experimental CAD program that the required tapering factor for minimum power-delay product in cascaded drivers of interconnection lines or trees is in the range 2-6 instead of 4-8 for a minimum delay View full abstract»

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  • Liquid-helium temperature hot-carrier degradation of Si p-channel MOSTs

    Page(s): 431 - 436
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    Results of a systematic study of the hot-carrier degradation of pMOSTs stressed at 4.2 K are reported. To a first approximation, the same shifts are observed as for room-temperature stress: a systematic increase in the drain current, both in linear operation and in saturation, caused by a positive shift of the threshold voltage. The transconductance is hardly affected for the devices and stress conditions studied. The substrate current is reduced in forward operation and increases for the reverse mode after stress. This degradation is partly removed by post-stress storage at room temperature. The results obtained point towards electron trapping in the oxide as the main degradation mechanism at 4.2 K in pMOSTs, although some interference with the substrate-related transient behaviour is observed View full abstract»

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