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Microwave Theory and Techniques, IEEE Transactions on

Issue 7 • Date July 2013

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  • Table of Contents

    Page(s): C1 - C4
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  • IEEE Transactions on Microwave Theory and Techniques publication information

    Page(s): C2
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  • Integration of Arbitrary Lumped Multiport Circuit Networks Into the Discontinuous Galerkin Time-Domain Analysis

    Page(s): 2525 - 2534
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2410 KB) |  | HTML iconHTML  

    A hybrid electromagnetic (EM) circuit simulator is proposed for incorporating multiport lumped circuit networks through their admittance matrices into the discontinuous Galerkin time-domain (DGTD) method. The admittance matrix in the Laplace domain can be derived analytically or obtained from network parameters such as S-parameters in the frequency domain. To convert frequency-dependent S-parameters into the admittance matrix in the Laplace domain, the vector-fitting technique is employed to facilitate the mapping process. The computational domain of interest is split into two subdomains. One is the EM part solved by the DGTD, and another is the circuit part modeled by the basic I-V relationships in the time domain. The couplings between the EM and circuit parts happen at lumped ports where the port voltages and currents are solved via these coupled systems. Due to the local properties of DGTD operations, only small coupling matrix equation systems are involved. To further improve the efficiency, local time-stepping strategy is included. To show the validity of the proposed simulator, several numerical examples are presented and compared with results from other references. View full abstract»

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  • An Efficient 2-D Compact Precise-Integration Time-Domain Method for Longitudinally Invariant Waveguiding Structures

    Page(s): 2535 - 2544
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    Based on both the compact technique and the precise-integration (PI) technique, a 2-D compact precise-integration time-domain method (CPITD) is developed in order to mitigate the rapidly growing numerical dispersion errors of a recently proposed compact finite-difference time-domain (FDTD) algorithm with increased time-step size when modeling electrically large and longitudinally invariant waveguiding structures. The stability condition and the dispersion equation of the new algorithm are both derived analytically. The provided enhancement over the FDTD, compact FDTD, and the conventional PITD methods is exhibited through theoretical examination of the dispersion performance, and subsequently, validated by means of numerical experimentation. It is found that with the PI technique, the maximum limit of the time step allowable by the new algorithm's stability criterion is much larger than the Courant-Friedrich-Levy limit of the compact-FDTD method, more particularly, numerical dispersion errors can be made nearly independent of time-step size, i.e., an appreciable reduction of numerical dispersion error is achievable at any time-step size in the simulations. Numerical experimentations of typical waveguide structures verify and validate the very promising theoretical results. This CPITD algorithm will be very useful in electrically large and longitudinally invariant waveguiding structures since the decreased number of grid points in the 2-D domain greatly reduces the memory requirements and also the overall computational time, and the PI technique nearly removes the impact of time-step size on the numerical dispersion, and as a consequence, significantly reduces numerical dispersion error for any time-step size. View full abstract»

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  • Analysis, Design, Modeling, and Characterization of Low-Loss Scalable On-Chip Transformers

    Page(s): 2545 - 2557
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    A few important design choices for a low-loss scalable on-chip transformer are discussed, the most important one being that the capacitive and inductive couplings should be aligned to minimize insertion loss. The importance of these design choices is illustrated both theoretically as well as experimentally. In particular, for the first time the performance of these on-chip transformers is verified with four-port S -parameter measurements taken up to 67 GHz. With that, an insertion loss of only 0.6 dB up to 30 GHz is demonstrated. To facilitate the use of these low-loss on-chip transformers in the RF integrated-circuit design flow, a scalable compact equivalent-circuit model suitable for all pre-layout circuit simulations is described, which accurately predicts transformation ratios, transmission efficiencies and balun amplitude and phase imbalances. View full abstract»

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  • Modeling Resonances in Transmission Lines Fabricated Over Woven Fiber Substrates

    Page(s): 2558 - 2565
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    This paper models transmission lines (TLs) fabricated over a printed circuit board substrate made of woven fiber fabric that causes resonances in the insertion and return loss. The modeling relies on the fact that these lines can be analyzed as periodically loaded TLs. Here, a method to determine the associated equivalent propagation constant and characteristic impedance is proposed. This allows to accurately reproduce the S-parameters for a TL of arbitrary length and for any periodicity of the fiber weave pattern along the line requiring neither multi-staged equivalent circuits, nor full-wave simulations. View full abstract»

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  • Direct Optimal Synthesis of a Microwave Bandpass Filter With General Loading Effect

    Page(s): 2566 - 2573
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    This paper presents a direct approach to the synthesis of a general Chebyshev bandpass filter that matches to a frequency variant complex load. The approach is based on the power wave renormalization theory and two practical assumptions, which are: 1) the prescribed transmission zeros are stationary and 2) the reflection zeros are located along the imaginary axis. Three necessary conditions that stipulate the characteristic polynomials associated to the filter are derived through renormalization of the load reference impedances. It has been shown that these three conditions can only be satisfied by an ideal filter circuit model separated by a piece of interconnecting stub from the complex load. The length of the stub will be optimally designed in the sense that the designed filter will best match to the complex load over a given frequency range. The proposed method offers a deterministic, yet flexible way for optimally designing a diplexer or a multiplexer with a realistic loading effect. The effectiveness of the method is demonstrated by two design examples. View full abstract»

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  • Tunable Bandpass Filter Design Based on External Quality Factor Tuning and Multiple Mode Resonators for Wideband Applications

    Page(s): 2574 - 2584
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    In this paper, a tunable bandpass filter using cross-shaped multiple mode resonators (MMRs) and N:1 transformer based external quality factor tuning structures is proposed. The use of a cross-shaped MMR simplifies inter-resonators control while two Qe tuning structures are investigated and incorporated with the MMR to implement simultaneous center frequency agility and narrow and wide bandwidth tuning. Compared with traditional tunable filters, the proposed architecture requires less tuning elements and is easier to realize wideband and high-order tunable filters. Two examples (Filter I and II) are presented to validate the design. Both filters use a single MMR and six tuning elements to achieve a third-order wideband tunable filter. Filter I reports 58% center frequency tuning with constant bandwidth and 14%-64.4% fractional bandwidth (FBW) tuning when center frequency locates at 1 GHz. Filter II achieves larger frequency agility and wider FBW tuning of 82.9% and 95%, respectively, for the same bandwidth and center frequency of Filter I. View full abstract»

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  • An Eight-Way Power Combiner Based on a Transition Between Rectangular Waveguide and Multiple Microstrip Lines

    Page(s): 2585 - 2593
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    This paper presents a broadband and low-loss power combiner based on a transition between eight microstrip lines and a rectangular waveguide. A tray-type structure is utilized in this design and all the trays are stacked up together along the narrow wall of the rectangular waveguide to take advantage of its uniform electric field distribution. The combiner has a wide bandwidth of 5.8-8.2 GHz, which is only limited by the operating frequency range of the WR-137 rectangular waveguide. The measured output return loss is better than 22 dB over the whole frequency range. The measured insertion loss of a back-to-back configuration is less than 0.78 dB, which is equivalent to a combining efficiency of 91.4% for a single combiner. The measured isolations between input ports are better than 12 dB. With eight microstrip input ports where three-terminal solid-state power amplifier devices are integrated and with a rectangular waveguide output port, the proposed structure is very suitable for high power-combining applications. View full abstract»

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  • Miniature Butler Matrix Design Using Glass-Based Thin-Film Integrated Passive Device Technology for 2.5-GHz Applications

    Page(s): 2594 - 2602
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2050 KB) |  | HTML iconHTML  

    In this paper, miniature branch-line coupler and Butler matrix designs for 2.5-GHz applications are proposed using the glass-based thin-film integrated passive device (TF-IPD) technology. The size reduction is achieved by replacing the quarter-wavelength transmission lines in a conventional branch-line coupler with the bridged-T coil. In this way, the circuit size can be largely reduced without sacrificing the operation bandwidth. The proposed miniature branch-line coupler is then applied to the design of a 4 × 4 Butler matrix centered at 2.5 GHz using the glass-based TF-IPD technology. The measured results show a bandwidth of 2.4-2.6 GHz for better than 13-dB return loss with a maximal dissipation of 4 dB, amplitude imbalance within 1.1 dB, and phase imbalance less than 13°. Notably, the proposed Butler matrix occupies a chip area of 3.13 mm × 3.3 mm, which is only about 0.026 λ0 × 0.027 λ0 at 2.5 GHz. View full abstract»

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  • Simulation of RF Power Distribution in a Packaged GaN Power Transistor Using an Electro-Thermal Large-Signal Description

    Page(s): 2603 - 2609
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1129 KB) |  | HTML iconHTML  

    A comprehensive electro-thermal model of a packaged GaN high electron-mobility transistor (GaN-HEMT) is presented. It includes an RF large-signal description, as well as thermal coupling between the individual cells of a powerbar. Thus, it allows studying the inhomogeneous RF power distribution and other effects within the transistor. The model is verified and applied to a 50-W GaN-HEMT powerbar. The model proves to represent a versatile tool for transistor design. Important features of the new version compared to existing versions are its capability to predict internal electrical instabilities and to allow for optimization of the cell combining. View full abstract»

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  • A Reconfigurable Integrated Dispersive Delay Line (RI-DDL) in 0.13-/spl mu/m CMOS Process

    Page(s): 2610 - 2619
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    This paper provides the theoretical analysis and physical implementation of a reconfigurable integrated dispersive delay line (RI-DDL) in the IBM 8RF 0.13-μm CMOS process. The RI-DDL employs a transversal filter structure, which is realized with the reverse gain port of a distributed amplifier. We successfully demonstrate that an RI-DDL is capable of achieving multiple nonuniform transmission line DDL transfer functions by altering the tap coefficients and polarities. The RI-DDL operates up to 4.5 GHz with 1.2-ns dispersion. We provide the experimental demonstration of the real time spectrum analysis (0.4-4 GHz) with the RI-DDL. Finally, we discuss the practical limitation of the proposed RI-DDL using the 0.13-μm CMOS process as well as the error bounds of the RI-DDL response due to discrete tap coefficient levels. View full abstract»

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  • An Ultra-Low Power V-Band Source-Driven Down-Conversion Mixer With Low-Loss and Broadband Asymmetrical Broadside-Coupled Balun in 90-nm CMOS Technology

    Page(s): 2620 - 2631
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3133 KB) |  | HTML iconHTML  

    This paper proposes a microwatt source-driven down-conversion mixer with broadband asymmetrical broadside-coupled baluns in a 90-nm CMOS low-power process. The forward body biased (FBB) technique reduces the threshold voltage (VTH) and supply voltage for operation in the near weak inversion region in millimeter-wave mixer designs. To effectively reduce the size of the chip, an asymmetrical broadside-coupled balun is developed with a bandwidth of 103 GHz (from 34 to 137 GHz) with a low insertion loss of 3.66 dB (3 dB for an ideal balun) at 58 GHz. The chip area of the balun is 0.016 mm2. The proposed FBB mixer has a 4.2-dB peak conversion gain and a 14.3-dBm input third-order intercept point at 55 GHz under a 2-dBm local-oscillator power. The dc power of the FBB mixer core is only 139 W, while it draws a 278-μA dc current from a 0.5-V supply. The fabricated FBB mixer, comprising two asymmetrical broadside-coupled baluns, and all of test pads and dummy blocks, occupies an area of 0.72 mm2. An FoMMixer1 that is obtained using the ultra-low power consumption FBB mixer is as high as 23.4. View full abstract»

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  • A 5-GHz CMOS LC Quadrature VCO With Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy

    Page(s): 2632 - 2640
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    This paper presents a quadrature voltage-controlled oscillator (QVCO) employing a proposed dynamic current-clipping coupling technique to provide around 90° phase shift in the coupling paths. The phase shift given by the coupling network not only improves the phase noise, but also desensitizes the phase error to component mismatches in the QVCO. The coupling network furthermore reduces the noise injected into the LC tank at the most vulnerable time (zero crossing points). The proposed current-clipping coupling allows the use of a strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1-MHz offset from a 5-GHz carrier. The QVCO consumes 4.2 mW from a 1-V power supply, resulting in an outstanding figure of merit of 189 dBc/Hz. View full abstract»

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  • A 77-GHz CMOS FMCW Frequency Synthesizer With Reconfigurable Chirps

    Page(s): 2641 - 2647
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1332 KB) |  | HTML iconHTML  

    This paper presents a 77-GHz CMOS frequency-modulated continuous-wave (FMCW) frequency synthesizer with the capability of reconfigurable chirps. The frequency-sweep range and sweep time of the chirp signals can be reconfigured every cycle such that the frequency-hopping random chirp signal can be realized for an FMCW radar transceiver. The frequency synthesizer adopts the fractional-N phase-locked-loop technique and is fully integrated in TSMC 65-nm digital CMOS technology. The silicon area of the synthesizer is 0.65 mm × 0.45 mm and it consumes 51.3 mW of power. The measured output phase noise of the synthesizer is -85.1 dBc/Hz at 1-MHz offset and the root-mean-square modulation frequency error is smaller than 73 kHz. View full abstract»

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  • Temperature-Compensated dB-linear Digitally Controlled Variable Gain Amplifier With DC Offset Cancellation

    Page(s): 2648 - 2661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2814 KB) |  | HTML iconHTML  

    This paper presents a compact digitally controlled variable gain amplifier (DVGA) with capabilities of both temperature compensated linear-in-decibel (dB-linear) gain control and dc offset cancellation (DCOC) without making use of either the feedback or the feed-forward loop. The proposed DVGA design is a three-stage inductorless cascaded amplifier that is integrated with a temperature-compensated dB-linear gain control, a DCOC, an output common mode feedback, a 6-bit digital gain control (with a 64-step resolution), a power shutdown mode, and a linearizer for improving the 1-dB gain compression point. The design is fabricated using a commercial 0.18-μm SiGe BiCMOS technology. The DVGA has a measured gain range of 18.4 dB with an average step size of 0.3 dB, a 3-dB bandwidth from 2 MHz to 1.9 GHz with a ±0.75-dB gain flatness from 2.75 MHz to 1.2 GHz, an input 1-dB gain compression point better than -12.5 dBm, an input return loss better than 12 dB, an output return loss better than 16 dB, and a dc power consumption of 12.2 mW from a 1.8-V supply. The core DVGA, by excluding the I/O measurement pads, occupies a die area of 160 μm × 300 μm. View full abstract»

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  • A 77-GHz CMOS Power Amplifier With a Parallel Power Combiner Based on Transmission-Line Transformer

    Page(s): 2662 - 2669
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1786 KB) |  | HTML iconHTML  

    This paper presents a 77-GHz CMOS power amplifier (PA) with a parallel power combiner based on a transmission-line transformer (TLT). An inter-stage matched cascode power cell structure is applied to obtain high output power and efficiency, where a simple matching network between the common-gate and common-source stage is introduced. The parallel power combiner based on a broadside-coupled TLT is analyzed and compared with a series power combiner. The PA is fabricated using a 65-nm RF CMOS process. It achieves the saturated output power of 15.8 dBm, the power-added efficiency of 15.2%, and the power gain of 20.9 dB with a supply voltage of 2.0 V at 77 GHz. View full abstract»

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  • V-Band High Data-Rate I/Q Modulator and Demodulator With a Power-Locked Loop LO Source in 0.15-/spl mu/m GaAs pHEMT Technology

    Page(s): 2670 - 2684
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4833 KB) |  | HTML iconHTML  

    A wideband sub-harmonically pumped (SHP) modulator and demodulator fabricated in 0.15-μm GaAs pseudomorphic high electron-mobility transistor technology are demonstrated in this paper. The chip is appropriate for emerging 60-GHz multi-gigabit communication applications. Digital modulation degradation resulting from in-phase/quadrature mismatch is effectively minimized by the proposed power-locked loop system. By overcoming the bandwidth limitations and quadrature errors in amplitude and phase, the sideband suppression ratio exhibits broadband performance with the feedback mechanism. By using the SHP mixer structure, the dc offset problem is mitigated because of decreased 2× local oscillator leakage. In addition, sub-circuit design considerations and feedback stability are described in this paper. The SHP modulator and demodulator demonstrate flat conversion-gain responses of -14 ±2 dB and -14 ±1 dB, respectively, from 51 to 68 GHz. Properties of multi-gigahertz modulation and demodulation bandwidths show the potentials for gigabit applications. The amplitude and phase imbalances are restricted within 0.3 dB and 5° (±2.5°), respectively, regardless of modulation or demodulation. High data-rate digital modulation and demodulation are successfully performed through 16-QAM and 64-QAM schemes within four channels of the IEEE 802.15.3c standard with outstanding error vector magnitude performances. View full abstract»

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  • Calibration-Kit Design for Millimeter-Wave Silicon Integrated Circuits

    Page(s): 2685 - 2694
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1776 KB) |  | HTML iconHTML  

    We study and present design guidelines for thru-reflect-line vector-network-analyzer calibration kits used for characterizing circuits and transistors fabricated on silicon integrated circuits at millimeter-wave frequencies. We compare contact-pad designs and develop fixed-fill contacts that achieve both repeatable and low contact-pad capacitances. We develop a fill-free and mesh-free transmission line structure for the calibration kit and compare it to similar transmission lines with meshed ground plane. We also develop a gold plating process that greatly improves contact repeatability, permitting the use of redundant multiline calibrations. This in turn simplifies the development of an error analysis. Finally, we apply the technique to state-of-the-art transistor characterization, and present measured results with uncertainties. View full abstract»

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  • A Load–Pull Characterization Technique Accounting for Harmonic Tuning

    Page(s): 2695 - 2704
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2110 KB) |  | HTML iconHTML  

    A novel methodology for the characterization of the nonlinear dynamic behavior of electron devices (EDs) is presented. It is based on a complete and accurate ED characterization that is provided by large-signal low-frequency I/V measurements, performed by means of a low-cost setup, in conjunction with any model-based description of the nonlinear reactive effects related to ED capacitances. The unique feature of the proposed technique is that a fully harmonic control of waveforms at the current generator plane is achieved, and as a consequence, high-efficiency operation can be simply investigated. Different experimental data are presented on GaAs and GaN transistors, and to definitely verify the capability of the new approach, the design of a class-F GaN power amplifier is deeply investigated as a case study. View full abstract»

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  • A Technique for the Measurement of the Generalized Scattering Matrix of Overmoded Waveguide Devices

    Page(s): 2705 - 2714
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1572 KB) |  | HTML iconHTML  

    A technique is described to measure the generalized scattering matrix (GSM) of a waveguide device whose ports are multimodal. The device-under-test is placed in between suitable converters, thereby transforming multimodal ports into monomodal ports. The needed data are then measured using a standard vector network analyzer. A dedicated algorithm is finally used to recover the multimode GSM of the device. The experimental validation is reported in this paper for rectangular and square waveguides showing excellent agreement between theory and measured results. View full abstract»

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  • Ambient RF Energy Harvesting in Urban and Semi-Urban Environments

    Page(s): 2715 - 2726
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB) |  | HTML iconHTML  

    RF harvesting circuits have been demonstrated for more than 50 years, but only a few have been able to harvest energy from freely available ambient (i.e., non-dedicated) RF sources. In this paper, our objectives were to realize harvester operation at typical ambient RF power levels found within urban and semi-urban environments. To explore the potential for ambient RF energy harvesting, a city-wide RF spectral survey was undertaken from outside all of the 270 London Underground stations at street level. Using the results from this survey, four harvesters (comprising antenna, impedance-matching network, rectifier, maximum power point tracking interface, and storage element) were designed to cover four frequency bands from the largest RF contributors (DTV, GSM900, GSM1800, and 3G) within the ultrahigh frequency (0.3-3 GHz) part of the frequency spectrum. Prototypes were designed and fabricated for each band. The overall end-to-end efficiency of the prototypes using realistic input RF power sources is measured; with our first GSM900 prototype giving an efficiency of 40%. Approximately half of the London Underground stations were found to be suitable locations for harvesting ambient RF energy using our four prototypes. Furthermore, multiband array architectures were designed and fabricated to provide a broader freedom of operation. Finally, an output dc power density comparison was made between all the ambient RF energy harvesters, as well as alternative energy harvesting technologies, and for the first time, it is shown that ambient RF harvesting can be competitive with the other technologies. View full abstract»

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  • A Batteryless RFID Remote Control System

    Page(s): 2727 - 2736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1499 KB) |  | HTML iconHTML  

    This paper presents a novel eco-friendly batteryless remote control (RC) system based on a multi-RF identification (RFID) scheme. The proposed RC device does not require the use of batteries or other installed power source. Instead, it relies on passive RFID chips that are remotely powered by an RFID reader. The controlled device (e.g., a TV) incorporates an RFID reader to power up and communicate with the RC. The proposed batteryless RC is composed of an antenna, a plurality of N passive RFID chips and N switches, and a multi-port microstrip network that interconnects the various RFID chips, allowing them to share a common antenna. Each key of the RC is associated to an RFID with a unique identifier, which allows the device to be controlled to identify the key pressed by the user. The proposed arrangement ensures that only the chip associated to the pressed key is read by the RFID reader, while the other chips remain inactive. First of all, the system is described including the multi-RFID scheme and the proposed multi-port network. Afterword, a characterization of the contact switches and RFID chips is performed. This is followed by RFID chip impedance matching and switch tuning. A multi-port network is fabricated (in low-cost FR4) and measured in order to access network's behavior depending on some parameters such as the number of ports and distance from the active port to the antenna. Finally, a four-key RC unit is prototyped, and an RFID reader system is integrated in a TV by using an external RFID-to-infrared interface. Four control functionalities are implemented and tested (CH+, CH-, Vol+, and Vol-). Measurements are also conducted to evaluate the system coverage range and line-of-sight capability. View full abstract»

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  • A 10-Gbit/s Wireless Communication Link Using 16-QAM Modulation in 140-GHz Band

    Page(s): 2737 - 2746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2202 KB) |  | HTML iconHTML  

    This paper describes a 140-GHz wireless link whose maximum transmission data rate is 10 Gbit/s. A sub-harmonic mixer and multiplier based on Schottky barrier diodes, a waveguide H ladder bandpass filter, a Cassegrain antenna, and other components have been developed to construct a high-performance transmitting and receiving front end. 16 quadrature amplitude modulation has been adopted to improve the spectrum efficiency to 2.86-bit/s/Hz. A 32-way parallel demodulation architecture based on frequency-domain implementation of the matched filter and timing phase correction is proposed. An adaptive blind equalization algorithm is also realized to enhance the tolerance for channel distortion. The modulated signal is centered at 140.3 GHz with -5-dBm output power. This link succeeded in transmission of a 10-Gbit/s signal over a 1.5-km distance with a bit error rate of 1e-6 in non-real-time mode. The measured 99.99% power bandwidth of the 10-Gbit/s signal is 3.6 GHz. The lowest acceptable signal noise rate per bit (Eb/N0) is 15 dB. This link also transmitted a 2-Gbit/s real-time signal with lowest BER = 1.80e -11. View full abstract»

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  • Corrections to "A novel distributed amplifier with high gain, low noise, and high output power in 18-μm cmos technology" [Apr 13 1533-1542]

    Page(s): 2747
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    There is an error in the order of the references [18] and [19] in the above-named article [ibid., vol. 61, no. 4, pp. 1533-1542, Apr. 2013]. The order of these references should be exchanged. The corrected order (and numbering) of these two references are shown as follows: [18] J. Kim and J. F. Buckwalter, "A 92 GHz bandwidth distributed amplifier in a 45 nm SOI CMOS technology," IEEE Microw. Wireless Compon. Lett., vol. 21, no. 6, pp. 329-331, Jun. 2011. [19] A. Jahanian and P. Heydari, "A CMOS distributed amplifier with distributed active input balun using GBW and linearity enhancing techniques," IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, pp. 1331-1341, May 2012. View full abstract»

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The IEEE Transactions on Microwave Theory and Techniques focuses on that part of engineering and theory associated with microwave/millimeter-wave components, devices, circuits, and systems involving the generation, modulation, demodulation, control, transmission, and detection of microwave signals. This includes scientific, technical, and industrial, activities. Microwave theory and techniques relates to electromagnetic waves usually in the frequency region between a few MHz and a THz; other spectral regions and wave types are included within the scope of the Society whenever basic microwave theory and techniques can yield useful results. Generally, this occurs in the theory of wave propagation in structures with dimensions comparable to a wavelength, and in the related techniques for analysis and design..

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