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IEE Proceedings - Computers and Digital Techniques

Issue 6 • Nov. 2006

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Displaying Results 1 - 4 of 4
  • Ant colony optimisation for task matching and scheduling

    Publication Year: 2006, Page(s):373 - 380
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (194 KB)

    PC clusters have recently received considerable interest as cost-effective parallel platforms for CPU-intensive applications. A cluster of PCs generally comprises of a collection of heterogeneous process elements (PEs). To make effective use of a PC cluster, a parallel program, which is characterised by a node- and edge-weighted directed acyclic graph (DAG), can usually be decomposed into a set of... View full abstract»

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  • Two-phase prediction of L1 data cache misses

    Publication Year: 2006, Page(s):381 - 388
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (264 KB)

    Hardware prefetching schemes which divide the misses into streams are generally preferred to other hardware based schemes. But, as they do not know when the next miss of a stream happens, they cannot prefetch a block in appropriate time. Some of them use a substantial amount of hardware storage to keep the predicted miss blocks from all streams. The other approaches follow the program flow and pre... View full abstract»

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  • LSQ: a power efficient and scalable implementation

    Publication Year: 2006, Page(s):389 - 398
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (300 KB)

    The load-store queue (LSQ) of modern superscalar processors is a critical and non-scalable component responsible for keeping the order of memory operations. As new architectures become more aggressive, the number of in-flight memory instructions increases, and the LSQ must satisfy higher capacity requirements. An efficient LSQ state filtering mechanism based on Bloom filtering is proposed, which, ... View full abstract»

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  • Efficient new approach for modulo 2/sup n/-1 addition in RNS

    Publication Year: 2006, Page(s):399 - 405
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (292 KB)

    A new modulo 2n-1 addition algorithm is presented, which is applicable in the residue number system. In contrast to previous work, the input carry in the first stage of the addition is set to one. The associated output carry is then used to conditionally modify the sum to produce the correct modulo 2n-1 result. Moreover, unlike recent adders in the literature, the result neve... View full abstract»

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Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

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