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VLSI for Parallel Processing, IEE Colloquium on

Date 17 Feb 1988

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Displaying Results 1 - 6 of 6
  • VLSI neural networks

    Publication Year: 1988, Page(s):7/1 - 7/4
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (236 KB)

    Strategies and design methods have been given for the construction of a hybrid analogue/digital VLSI neural network chip and a bit-serial VLSI network and board. Bit-serial and `reduced-style' arithmetic enhances the level of integration beyond more conventional digital, bit-parallel schemes. The restrictions imposed on both synaptic weight size and arithmetic precision by VLSI constraints have be... View full abstract»

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  • A parallel processing system for real-time image generation using RISC-like microprocessors

    Publication Year: 1988, Page(s):6/1 - 6/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper presents a parallel processing system for real-time image generation (RTIG) that employs RISC-like microprocessors to perform geometric computations. It also demonstrates that tuned application-oriented processors can achieve performance ratios superior by one order of magnitude, when compared to the performance achieved by general-purpose processors applied to the same problem. The arc... View full abstract»

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  • IEE Colloquium on `VLSI for Parallel Processing' (Digest No.27)

    Publication Year: 1988
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (28 KB)

    The following topics were dealt with: role of optics in parallel processing; limitations facing VLSI parallel processors; architectural considerations for a wafer scale processor; WSI architecture for AI semantic networks; parallel processing system for real-time image generation using RISC-like microprocessors; and VLSI neural networks. Abstracts of individual papers can be found under the releva... View full abstract»

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  • The role of optics in parallel processing

    Publication Year: 1988, Page(s):3/1 - 3/5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (232 KB)

    The author has recently been involved in trying to predict the specific technical areas where optical technology will next make a major technical and economic impact in advanced computer systems. This paper discusses some of the overall issues and highlights two new examples which he believes are likely to be important on a fairly short timescale. Because both basic physics and known device techno... View full abstract»

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  • Architectural considerations of a wafer scale processor

    Publication Year: 1988, Page(s):4/1 - 4/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (192 KB)

    This paper describes some of the work carried out by British Telecom, and partners, as part of the European collaborative project ESPRIT 824. The project is developing a number of wafer scale devices including a single instruction multiple data (SIMD) processor array, with a target performance of 60000 MIPs. The intention is that there will be 128*128 working processing elements on each 4" wafer. ... View full abstract»

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  • A WSI architecture for AI semantic networks

    Publication Year: 1988, Page(s):517 - 514
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (152 KB)

    Many artificial intelligence (AI) applications need high performance computers that allow them to execute algorithms at reasonable speed. In recent years, researchers at universities and industry have developed new architectures in order to accomplish the performance required. A number of the AI algorithms require knowledge representation and manipulation which can be obtained by means of semantic... View full abstract»

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