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Proceedings 1988 IEEE International Conference on Computer Design: VLSI

3-5 Oct. 1988

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Displaying Results 1 - 25 of 125
  • Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '88 (Cat. No.88CH2643-5)

    Publication Year: 1988, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (346 KB)
    Freely Available from IEEE
  • Estimation of area and performance overheads for testable VLSI circuits

    Publication Year: 1988, Page(s):402 - 407
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochasti... View full abstract»

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  • The Astronautics ZS-1 processor

    Publication Year: 1988, Page(s):307 - 310
    Cited by:  Papers (1)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The Astronautics ZS-1 is a high speed minisupercomputer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture which splits instruction words into two streams, one for fixed-point/memory-address computation and the other for floating-point operations. The two instruction streams are then processed in parallel, with architectural queues... View full abstract»

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  • System interface of the NS32532 microprocessor

    Publication Year: 1988, Page(s):232 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    The NS32532 system interface eases system design while maximizing its performance potential. Various design techniques enable the interface to improve CPU access time during cache misses and write cycles. The interface also speeds system design and performance needs of different systems. The basic memory cycle, system debug features, and application support are discussed in detail View full abstract»

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  • Potential applications of high-Tc superconducting transmission lines in integrated systems

    Publication Year: 1988, Page(s):172 - 177
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Simple models and formulas characterizing pulse propagation over superconducting microstrip transmission lines are summarized. The models consider the phase velocity and attenuation coefficient of high-T c superconducting microstrip lines. Two examples, one involving a high-bandwidth interconnect bus for a time-multiplexed fine-grained multiprocessor, and the other an electrica... View full abstract»

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  • The Cydra 5 computer system architecture

    Publication Year: 1988, Page(s):302 - 306
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    An overview of the Cydra 5 computer system architecture is presented. A single numeric processor and multiple interactive processors are used to provide sustained compute performance in numeric applications. The numeric processors' unique directed dataflow architecture supports the parallelization of a much broader range of algorithms than vector processor architectures. Applications can be ported... View full abstract»

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  • A comparison of two digit serial VLSI adders

    Publication Year: 1988, Page(s):227 - 229
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level descrip... View full abstract»

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  • Analog circuit synthesis and exploration in OASYS

    Publication Year: 1988, Page(s):44 - 47
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Experimental results obtained with OASYS, a behavior-to-structure synthesis tool for analog circuits, are described. In particular, measurements from fabricated analog ICs based on OASYS-synthesized designs are presented, and used to verify that OASYS is capable of producing real, functional circuits. Possibilities for automatically exploring the space of designable analog circuits, an ability mad... View full abstract»

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  • A higher level hardware design verification

    Publication Year: 1988, Page(s):596 - 599
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    A novel approach to formal verification of computer hardware designs at a higher level of representation than the register-transfer level is presented. In this verification method, the specification of a digital system is defined as the input/output behavior of the external systems that communicate with the target system. The specification description called a cospecification and the implementatio... View full abstract»

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  • Super computer technology at Convex

    Publication Year: 1988, Page(s):16 - 20
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Several key design aspects of the Convex C Series supercomputer are presented. In particular, some of the key tradeoffs involved in the use of application-specific integrated-circuit (ASIC) devices are discussed. These include tradeoffs with respect to device power and technology, and where within the system ASIC devices were used as opposed to SSI/MSI devices. An overview of the simulation method... View full abstract»

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  • Tera-Hertz study of normal and superconducting transmission lines

    Publication Year: 1988, Page(s):168 - 171
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Electrical pulses as short as 0.6 ps in duration have been generated and sampled on coplanar transmission lines made of normal metals and superconductors to study the dispersion and loss spectrum in the frequency range up to 1 THz. The superconducting lines are superior when the loss of their normal metal counterparts is dominated by the resistance. However, the strong dispersion induced by the su... View full abstract»

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  • Gate array technology

    Publication Year: 1988, Page(s):296 - 299
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates. The author discusses gate arrays in terms of basic technology, complexity evolution, array architecture, process technology, and packaging... View full abstract»

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  • Approaching a nanosecond: a 32 bit adder

    Publication Year: 1988, Page(s):221 - 226
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/tec... View full abstract»

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  • High speed, low power CMOS transmitter-receiver system

    Publication Year: 1988, Page(s):344 - 347
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A CMOS transmitter-receiver system is described which has a limited voltage swing output. This system has high performance and low power dissipation. The measured worst-case frequency occurs near the 200-MHz range while the ADVICE projected best-case fast frequency is 600 MHz. This system also has the capability of functioning down to DC View full abstract»

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  • A self-reconfiguration scheme for fault-tolerant VLSI processor arrays

    Publication Year: 1988, Page(s):560 - 563
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    An interconnection network capable of spontaneously reconfiguring a VLSI processor array upon detection of faulty processors is presented. Although the reconfiguration process is global in nature, the network control circuitry is localized around each processor and is therefore completely modular. In effect, the switches and control circuitry are completely local to each processing element (PE) ev... View full abstract»

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  • Floating point CORDIC for matrix computations

    Publication Year: 1988, Page(s):40 - 42
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The Coordinate Rotation Digital Computer (CORDIC) algorithms provide a VLSI hardware technique for computing the inverse tangents and vector rotations needed by many matrix decomposition algorithms. A novel simplified CORDIC processor composed of floating-point data paths with a fixed-point angle calculation is proposed. This hybrid processor possesses sufficient accuracy for matrix computations s... View full abstract»

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  • A functional approach to formal hardware verification: the MTI experience

    Publication Year: 1988, Page(s):592 - 595
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors present the application of formal verification techniques to the MTI (Microprocesseur a test integre) microprocessor. The device is described and verified using a functional model. The authors note that the application is a real, rather than a verification-oriented microprocessor, whose description was available to them under the form of schematic and timing diagrams and as output of C... View full abstract»

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  • Test generation in a parallel processing environment

    Publication Year: 1988, Page(s):11 - 14
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The availability of low-cost, high-performance, general-purpose parallel machines has made parallel processing viable for the development of CAD (computer-aided design) applications. The authors identify the key issues that surface when an attempt is made to parallelize the test-generation process. They illustrate how different test-generation strategies can be mapped onto different classes of par... View full abstract»

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  • SID: synthesis of integral design

    Publication Year: 1988, Page(s):204 - 208
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The author describes the SID program, a knowledge-based expert system used for the synthesis of logic designs. A system architecture is presented with several major contributions: synthesis is performed on heterogeneous sets of logic elements in their natural physical partitions. Logic design database and rule language are customized to give rules complete decision and transformation capabilities ... View full abstract»

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  • RISC architecture of the M88000

    Publication Year: 1988, Page(s):370 - 373
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The 88000 processor family is one of the RISC (reduced-instruction-set computer) microcomputers that integrate the integer execution unit, the floating-point unit, the instruction fetch pipelines, and a data memory unit interface onto a single device. There are many supporting structures, such as advance branch target address calculation, dedicated units for memory address calculation, and bit fie... View full abstract»

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  • The design of the VLSI image-generator ZaP

    Publication Year: 1988, Page(s):163 - 166
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The authors present the design of `zoom and pan' (ZaP), a complex 160K-transistor delay-insensitive VLSI circuit. ZaP generates images from structured geometric data with a performance of a million boxes per second. A VLSI program is derived from a formal specification of ZaP though stepwise refinement and decomposition. The subsequent silicon compilation is described briefly. It is concluded that... View full abstract»

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  • Large memory embedded ASICs

    Publication Year: 1988, Page(s):292 - 295
    Cited by:  Papers (8)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Application-specific integrated circuits (ASICs) with high-performance embedded memory array with suitable design route have considerable merits in terms of system speed, scalability with technology and system cost. The choice of design approach according to applications is critical. For highly memory-rich applications, one of the recently developed memory ASICs, an integrated cache memory is desc... View full abstract»

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  • Critic: a knowledge-based program for critiquing circuit designs

    Publication Year: 1988, Page(s):324 - 327
    Cited by:  Papers (7)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Critic is a knowledge-based system that looks for errors or `bad design style' in circuit designs. Critic takes as input a description of a circuit and a knowledge-base that describes a particular design-style and technology. The knowledge base consists of: process and design-style constants, a set of primitive descriptions, a set of structure descriptions, and error-checking rules. Critic uses th... View full abstract»

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  • Generation of high speed CMOS multiplier-accumulators

    Publication Year: 1988, Page(s):217 - 220
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace-tree-based multiplier-accumulators (MACs). MAGGEN generates optimized netlists and compact layouts for MACs. MAGGEN's fast parallel MAC design is achieved through timing optimization routines. Compact layout, on the other hand, is achieved through prudent floorplanning, ma... View full abstract»

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  • Representation of control and timing behavior with applications to interface synthesis

    Publication Year: 1988, Page(s):382 - 387
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than som... View full abstract»

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