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Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Date 3-5 Oct. 1988

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  • Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '88 (Cat. No.88CH2643-5)

    Publication Year: 1988, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (346 KB)
    Freely Available from IEEE
  • Limits of backplane bus design

    Publication Year: 1988, Page(s):236 - 239
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The author examines the fundamental design parameters of backbone interconnection including: architecture, synchronization, bus width, protocols, arbitration, and the transmission medium. The theoretical limits to the bus performance are examined along with type of system and information-flow organization that can allow effective utilization of the available bandwidth. The two technology-dependent... View full abstract»

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  • System interface of the NS32532 microprocessor

    Publication Year: 1988, Page(s):232 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    The NS32532 system interface eases system design while maximizing its performance potential. Various design techniques enable the interface to improve CPU access time during cache misses and write cycles. The interface also speeds system design and performance needs of different systems. The basic memory cycle, system debug features, and application support are discussed in detail View full abstract»

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  • A comparison of two digit serial VLSI adders

    Publication Year: 1988, Page(s):227 - 229
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level descrip... View full abstract»

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  • Approaching a nanosecond: a 32 bit adder

    Publication Year: 1988, Page(s):221 - 226
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/tec... View full abstract»

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  • Implementation of fast radix-4 division with operands scaling

    Publication Year: 1988, Page(s):486 - 489
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A radix-4 divider can potentially achieve a speedup of two with respect to a radix-2 implementation by halving the number of steps. However, the complicated quotient-digit selection function increases the critical path and almost eliminates the speedup. The authors present an implementation of a scheme that scales the divisor close to unity, making the quotient-selection function independent of th... View full abstract»

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  • Test generation of C-testable array dividers

    Publication Year: 1988, Page(s):140 - 144
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The design of C-testable array dividers that are tested with a test set of constant length irrespective of the circuit size is presented. The results show that the proposed designs of n-by- n nonrestoring and restoring array dividers are C-testable and can be fully tested using only 20 and 40 test patterns, respectively. Algorithms that generate the test patterns and expected out... View full abstract»

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  • Generation of high speed CMOS multiplier-accumulators

    Publication Year: 1988, Page(s):217 - 220
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace-tree-based multiplier-accumulators (MACs). MAGGEN generates optimized netlists and compact layouts for MACs. MAGGEN's fast parallel MAC design is achieved through timing optimization routines. Compact layout, on the other hand, is achieved through prudent floorplanning, ma... View full abstract»

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  • Set-associative dynamic random access memory

    Publication Year: 1988, Page(s):478 - 483
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Static-column dynamic RAMs (random-access memories) offer fast access to successive locations within a single row, a fact which has been used in their implementation in fast cacheless memory systems. Such caches are necessarily nonassociative (direct-mapped), limiting their performance relative to set-associative caches of similar total capacity. The authors describe an architecture for dynamic RA... View full abstract»

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  • A class of fault-tolerant cellular permutation networks

    Publication Year: 1988, Page(s):136 - 139
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A scheme for fault-tolerant triangular cellular interconnection networks is proposed. A fault model is defined which unifies the concept of usable and unusable faulty components. An algorithm for testing these networks with a minimal number of tests (8) is presented. This result is extended to other cellular networks. A constant number of tests independent of the network size (at most 8) is added,... View full abstract»

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  • Super computer technology at Convex

    Publication Year: 1988, Page(s):16 - 20
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Several key design aspects of the Convex C Series supercomputer are presented. In particular, some of the key tradeoffs involved in the use of application-specific integrated-circuit (ASIC) devices are discussed. These include tradeoffs with respect to device power and technology, and where within the system ASIC devices were used as opposed to SSI/MSI devices. An overview of the simulation method... View full abstract»

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  • Error tolerance in parallel simulated annealing techniques

    Publication Year: 1988, Page(s):545 - 548
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The authors present some statistical properties of the error introduced in a parallel annealing algorithm for placement. A general parallel algorithm model not specific to any target-machine implementation has been proposed. They have characterized the error in such a general parallel paradigm. Further, they have shown how this error varies with temperature for different parallel configurations. S... View full abstract»

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  • Design of a high-speed arithmetic datapath

    Publication Year: 1988, Page(s):214 - 215
    Cited by:  Papers (8)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    This paper presents the implementation of a 64/32 bit floating-point datapath circuit (WTL3×64). This high-speed CMOS circuit integrates a 2 Kbit six-port register file, an independent 64/32-bit alu, a multiplier, and a divide/square-root unit for IEEE binary floating-point format numbers. It is fabricated using a 1.2 micron two-layer-metal CMOS technology. Operating at 60 ns cycle time, the... View full abstract»

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  • A methodology for the control and custom VLSI implementation of large-scale Clos networks

    Publication Year: 1988, Page(s):472 - 477
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A control algorithm is developed and implemented for a three-stage Clos network which results in using a multiple-chip approach. The system will be nonblocking in the strict sense and completely self-routing, i.e. the controller for the network will reside in the network and not in a separate computer that runs a program that controls switches to the interconnect array. Intermodule communication r... View full abstract»

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  • Parallel LU factorization for circuit simulation on an MIMD computer

    Publication Year: 1988, Page(s):129 - 132
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Direct method circuit simulation on an MIMD (multiple-instruction, multiple-data-stream) machine is studied. The focus is on the parallel LU (lower-upper) factorization a sparse matrix with a nested bordered-block diagonal (BBD) ordering. A novel computation model for the parallel factorization is proposed, and simulation results conducted on a ten-processor Sequent Balance 21000 parallel computer... View full abstract»

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  • Test generation in a parallel processing environment

    Publication Year: 1988, Page(s):11 - 14
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The availability of low-cost, high-performance, general-purpose parallel machines has made parallel processing viable for the development of CAD (computer-aided design) applications. The authors identify the key issues that surface when an attempt is made to parallelize the test-generation process. They illustrate how different test-generation strategies can be mapped onto different classes of par... View full abstract»

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  • Simulated annealing on a multiprocessor

    Publication Year: 1988, Page(s):540 - 544
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors present a method for parallelizing the simulated annealing algorithm by mapping the algorithm onto a dynamically structured tree of processors. The resulting parallel simulated annealing algorithm is discussed and its performance evaluated using simulation techniques. An important property of the parallel algorithm is that it maintains the same move decision sequence as the serial simu... View full abstract»

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  • Automatic layout and optimization of static CMOS cells

    Publication Year: 1988, Page(s):180 - 185
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A novel algorithm for generating complex CMOS gates from Boolean factored forms is presented. It uses a hierarchical composition of cells corresponding to the subexpressions of a Boolean factored form. Composition rules that allow for constructing the gates in linear time are derived. Cell width/height tradeoffs are made possible to ease pitch-matching. The algorithm has been coded in a pair of pr... View full abstract»

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  • Analog circuit synthesis and exploration in OASYS

    Publication Year: 1988, Page(s):44 - 47
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Experimental results obtained with OASYS, a behavior-to-structure synthesis tool for analog circuits, are described. In particular, measurements from fabricated analog ICs based on OASYS-synthesized designs are presented, and used to verify that OASYS is capable of producing real, functional circuits. Possibilities for automatically exploring the space of designable analog circuits, an ability mad... View full abstract»

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  • The KARL/KARATE system-integrating functional test development into a CAD environment for VLSI

    Publication Year: 1988, Page(s):209 - 212
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    KARATE is a system for testability analysis and automatic test pattern generation. It is embedded in the KARL design environment. Like the KARL environment, KARATE works on hardware descriptions at RT, gate, and switch level. A comfortable, interactive user interface makes the process of test-pattern generation transparent to the user. Badly controllable or badly observable hardware components or ... View full abstract»

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  • A coprocessor with supercomputer capabilities for personal computers

    Publication Year: 1988, Page(s):468 - 471
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The architecture of a matrix product coprocessor with supercomputer capabilities is described. It consists of a three-chip set requiring two custom VLSI chip designs, and a 50-ns memory subsystem and associated software drivers. One chip design implements a reconfigurable systolic array of simple processing elements, and the other provides both a generic interface to a host processor and schedules... View full abstract»

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  • Multi-chip packaging for high performance systems

    Publication Year: 1988, Page(s):76 - 81
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Multichip module (MCM) substrate, component assembly, and cooling technologies have been developed and demonstrated on several vehicles that include a 4-Kbyte RAM module operating at above 100-MHz clock frequency. An optimum MCM may consist of a set of composite layers of a multi-layer thin film polyimide structure over a multilayer ceramic substrate with a high pin density. The MCM technology pro... View full abstract»

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  • Representation of control and timing behavior with applications to interface synthesis

    Publication Year: 1988, Page(s):382 - 387
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than som... View full abstract»

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  • Variable reduction in MOS timing models

    Publication Year: 1988, Page(s):124 - 128
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    It is shown how careful parameter reduction can be used to produce simple but very accurate macromodels for complex logic circuits. To model input and output voltage waveforms, the authors use approximations that are time-scaled and time-shifted versions of `typical' waveforms rather than highly simplified waveforms such as ramps. To model devices, they use scaled nonlinear characteristics. Furthe... View full abstract»

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  • CESAR-A programmable high performance systolic array processor

    Publication Year: 1988, Page(s):414 - 417
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The authors describe the architecture and implementation of the CESAR computer system. The computing unit in CESAR has from one to four programmable systolic arrays working strictly in parallel, representing a SIMD (single-instruction multiple-data) structure. Each array consists of 128 custom-designed processing elements individually programmable for performing bit-serial operations on 32-bit dat... View full abstract»

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