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Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Date 3-5 Oct. 1988

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  • Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '88 (Cat. No.88CH2643-5)

    Publication Year: 1988 , Page(s): 0_1
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    Freely Available from IEEE
  • ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovations

    Publication Year: 1988 , Page(s): 611 - 614
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    The author describes how IBM's most powerful system achieved significant growth through a balance of technology use and systems design. Selective use of a novel advanced transistor technology combined with innovative processor-design techniques solved many system design limitations. The author examines several system design problems and the solutions. He describes how a broad spectrum of systems architecture environments were enhanced and how significant data path improvements resulted in very high throughput and fast response time. Issues discussed are the writable control store, active address spaces, and the improvement of data-sharing performance View full abstract»

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  • Tera-Hertz study of normal and superconducting transmission lines

    Publication Year: 1988 , Page(s): 168 - 171
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    Electrical pulses as short as 0.6 ps in duration have been generated and sampled on coplanar transmission lines made of normal metals and superconductors to study the dispersion and loss spectrum in the frequency range up to 1 THz. The superconducting lines are superior when the loss of their normal metal counterparts is dominated by the resistance. However, the strong dispersion induced by the superconducting gap limits their usefulness to below the gap frequency, which is about 0.7 THz for superconducting Nb, and maybe as high as 16 THz for high-Tc superconducting oxides View full abstract»

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  • Potential applications of high-Tc superconducting transmission lines in integrated systems

    Publication Year: 1988 , Page(s): 172 - 177
    Cited by:  Papers (1)
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    Simple models and formulas characterizing pulse propagation over superconducting microstrip transmission lines are summarized. The models consider the phase velocity and attenuation coefficient of high-T c superconducting microstrip lines. Two examples, one involving a high-bandwidth interconnect bus for a time-multiplexed fine-grained multiprocessor, and the other an electrical time-delay element in the femtosecond regime, are presented View full abstract»

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  • EXIST: an interactive VLSI architectural environment

    Publication Year: 1988 , Page(s): 312 - 319
    Cited by:  Papers (2)  |  Patents (1)
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    EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers View full abstract»

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  • An octagonal geometry compactor

    Publication Year: 1988 , Page(s): 190 - 193
    Cited by:  Patents (13)
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    Layout compactors have been widely adopted by symbolic layout systems to compact circuit layout. A common limitation among current state-of-the-art compactors is that they can only compact orthogonal geometries. The author describes a one-dimensional compactor that can compact arbitrary octagonal geometries. The compactor is based on the constraint graph approach. The octagonal geometry compactor offers significant area saving over the orthogonal geometry compactors when 45°-angle wires and edges are involved. The algorithms to compact 45- and 90° -angle geometries are described View full abstract»

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  • Automatic layout and optimization of static CMOS cells

    Publication Year: 1988 , Page(s): 180 - 185
    Cited by:  Papers (12)
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    A novel algorithm for generating complex CMOS gates from Boolean factored forms is presented. It uses a hierarchical composition of cells corresponding to the subexpressions of a Boolean factored form. Composition rules that allow for constructing the gates in linear time are derived. Cell width/height tradeoffs are made possible to ease pitch-matching. The algorithm has been coded in a pair of programs, called Castor and Pollux. The programs have been used to generate moderately complex layouts, consisting of circuits having up to a few thousand transistors. They can also be used to automatically generate a library of logic gates View full abstract»

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  • A matched-delay CMOS TDM multiplexer cell

    Publication Year: 1988 , Page(s): 352 - 355
    Cited by:  Papers (4)  |  Patents (1)
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    Standard time-division multiplexer circuits use variations on a finite-state-machine approach to sequence through all input data. The authors present an alternate multiplexer architecture that avoids both the bottleneck of waiting for latches to settle and the problems of distributing a high-frequency clock signal. The authors have investigated the tradeoffs between various architectures by fabricating and testing a CMOS implementation of both a matched-delay and shift-register-based architecture. Experiments show that the proposed approach can be competitive, but additional experiments are needed to further understand its practical limits View full abstract»

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  • The Cydra 5 computer system architecture

    Publication Year: 1988 , Page(s): 302 - 306
    Cited by:  Papers (1)  |  Patents (1)
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    An overview of the Cydra 5 computer system architecture is presented. A single numeric processor and multiple interactive processors are used to provide sustained compute performance in numeric applications. The numeric processors' unique directed dataflow architecture supports the parallelization of a much broader range of algorithms than vector processor architectures. Applications can be ported to the Cydra 5 and achieve very high performance with significantly less reprogramming than on alternative architectures. The numeric processor requires significantly less application reprogramming to make efficient use of its architecture to accelerate typical numeric applications. The numeric processor parallelizes programs with recurrences, conditionals within loops, unstructured memory reference, and other difficult-to-vectorize program constructs View full abstract»

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  • Design of a high-speed arithmetic datapath

    Publication Year: 1988 , Page(s): 214 - 215
    Cited by:  Papers (8)  |  Patents (18)
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    This paper presents the implementation of a 64/32 bit floating-point datapath circuit (WTL3×64). This high-speed CMOS circuit integrates a 2 Kbit six-port register file, an independent 64/32-bit alu, a multiplier, and a divide/square-root unit for IEEE binary floating-point format numbers. It is fabricated using a 1.2 micron two-layer-metal CMOS technology. Operating at 60 ns cycle time, the 165000 transistor/147600 square mil chip provides 33 double-precision Mflops of peak performance. The register file, together with special registers, a flexible input/output interface, features for high level language support, and 1.5 Watts of power facilitate ease of integration of the device into various computer systems View full abstract»

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  • Classical fault analysis for MOS VLSI circuits

    Publication Year: 1988 , Page(s): 277 - 282
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    Due to the high cost associated with generating effective input vectors to test MOS circuits, finding ways to reduce this test vector generation cost is of considerable interest. Empirical results show that fault coverage obtained from MOS transistor-level fault simulation using randomly generated test inputs can be approximated by the fault coverage obtained using the test vectors generated from classical stuck-at-zero and stuck-at-one fault simulation on logic-gate-level circuits. Applying this result, an approach is presented to reduce the cost of test vector generation for MOS circuits View full abstract»

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  • The MIPS M2000 system

    Publication Year: 1988 , Page(s): 366 - 369
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    The M2000 represents an attempt to design a system optimized to support a RISC (reduced-instruction-set computer) processor. While RISC processors in general have a high memory-bandwidth requirement, the R3000 through the use of data block refill, instruction streaming, and write streaming has been tuned to require yet more bandwidth. This tuning is reflected in its 1.25 average cycles per instruction. The M2000 attacks the memory-bandwidth problem by extensive use of page-mode DRAMs (dynamic random-access memory) for all memory accesses: processor reads, processor writes, I/O reads, and I/O writes, using page-mode access. Where a bandwidth mismatch is present, i.e. between the I/O bus and the memory array. FIFO (first-in, first out) buffering is provided to prevent memory tieup View full abstract»

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  • PARET; an integrated visual tool for the study of parallel systems

    Publication Year: 1988 , Page(s): 320 - 323
    Cited by:  Papers (1)
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    PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative architectural decisions and experiments with such issues as scheduling, mapping, and routing policies. PARET is unique in providing an animated interactive visual tool for parallel systems with a modeling paradigm that is closely linked to its graphical representation. Models have the same morphology regardless of the subsystem represented or the level of detail in the model. Presently, PARET runs on SUN workstations, using color graphics, mouse input, and pop-up menus to control and observe a simulation engine. Ongoing projects using PARET include evaluation of a special-purpose multiprocessor system and use of PARET in a system to create application-specific ICs for signal processing View full abstract»

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  • Processor design using path programmable logic

    Publication Year: 1988 , Page(s): 196 - 199
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    Path programmable logic (PPL) is a VLSI design methodology that is very efficient in the implementation of systems consisting of random logic, counters, and finite-state machines. Previous designs have shown that PPL does not efficiently allow the implementation of bus-oriented designs, such as microprocessors, arithmetic processors, and DSP (digital signal processor) chips. The authors present solutions that enable these architectures to be implemented more efficiently. The solutions are the introduction of automated routing and placement tools as well as the description of sophisticated PPL library cells. The implementation of a RISC (reduced-instruction-set computer) processor is used as a case study to verify the effectiveness of these changes to the existing PPL methodology View full abstract»

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  • A modular VLSI architecture for coincidence detection in positron emission tomography

    Publication Year: 1988 , Page(s): 464 - 467
    Cited by:  Papers (1)
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    A VLSI architecture for a portion of the processing required to reconstruct images for positron emission tomography is described. Implementing this architecture in VLSI not only reduced the size and cost of the circuitry but also reduced the length requirements of an expensive high-speed cable. The architecture was practical only in VLSI since it required a large number of internal connections. However, the silicon area needed for making these connections was minimized by using nearest-neighbor communication within the array of modules. Furthermore, the design complexity of the architecture was kept manageable by replicating a single module 56 times within the array View full abstract»

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  • Stop criteria in simulated annealing

    Publication Year: 1988 , Page(s): 549 - 552
    Cited by:  Papers (4)
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    The authors propose stopping criteria based on statistics collected during the annealing. In contrast to conventional stop criteria, the proposed criteria do not depend on the move set. Specifically, formulae are presented for detecting that an adequate final temperature has been reached. The arguments of the formulae are obtained by observing the behavior of the variance of the score for the instance at hand. The formulae are based on experience with several applications of simulated annealing as well as facts derived from the theory of homogeneous Markov chains View full abstract»

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  • Test generation in a parallel processing environment

    Publication Year: 1988 , Page(s): 11 - 14
    Cited by:  Papers (26)
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    The availability of low-cost, high-performance, general-purpose parallel machines has made parallel processing viable for the development of CAD (computer-aided design) applications. The authors identify the key issues that surface when an attempt is made to parallelize the test-generation process. They illustrate how different test-generation strategies can be mapped onto different classes of parallel machines, including loosely coupled distributed systems, distributed-memory systems with message-passing architectures, and tightly coupled multiprocessor systems with shared global memory. Parallel test generation using a single heuristic and using multiple heuristics is considered. The performance of these mapping strategies is predicted by using uniprocessor turnaround times and an estimate of the communication delays View full abstract»

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  • VLSI support for copyback caching protocols on Futurebus

    Publication Year: 1988 , Page(s): 240 - 246
    Cited by:  Patents (5)
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    The author discusses the nature of the superset of copyback cache protocols described by the MOESI state model, the superset bus transactions of the Futurebus, and the complications encountered in an actual VLSI implementation. It has been shown that the Futurebus provides the best generic and standard solution to cost-effective interconnection of coherent copyback caches. Its fully compelled protocol and the ability to extend or abort transactions allowed the design of the cache controller to be much simpler and less subject to critical timing constraints that it would otherwise have been. The practical design details of the cache controller uncovered numerous coherence `holes' involving data that is in transit in the fill or flush buffer, or that is partially within the SRAM (static random-access memory) array and partially within the fill buffer. These were solved by thinking of those buffers as one-line caches, with cache state (such as ownership) associated with them View full abstract»

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  • Optimization for automatic cell assembly

    Publication Year: 1988 , Page(s): 186 - 189
    Cited by:  Papers (1)
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    The authors describe an implementation of a cell assembler which automatically decides if the connections between two cells should be made by abutting the cells or by inserting jogged wires. The assembly problem is treated as a two-dimensional river routing problem and is solved by constructing constraint graphs. Experimental results are given which show area reduction due to automatic jogging View full abstract»

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  • VLSI implementation of GSC architecture with a new ripple carry adder

    Publication Year: 1988 , Page(s): 520 - 523
    Cited by:  Papers (5)
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    The authors describe the VLSI implementation of a general sidelobe cancellor (GSC) using powers-of-two arithmetic. The chip needed for this design carries six multiplications and seven additions. The layout of this chip is based on the standard cell and regular structure approach. To reduce the propagation delay of its carry-save addition unit, a fast ripple carry adder which has a single NAND gate delay for carry propagation is designed. This adder is designed to reduce the propagation delay of carries by a factor of two View full abstract»

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  • Simulated annealing on a multiprocessor

    Publication Year: 1988 , Page(s): 540 - 544
    Cited by:  Papers (3)
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    The authors present a method for parallelizing the simulated annealing algorithm by mapping the algorithm onto a dynamically structured tree of processors. The resulting parallel simulated annealing algorithm is discussed and its performance evaluated using simulation techniques. An important property of the parallel algorithm is that it maintains the same move decision sequence as the serial simulated annealing algorithm, thus avoiding problems associated with move conflicts and erroneous move acceptance/rejection decisions which have been associated with other parallel simulated annealing algorithm proposals. The parallel algorithm presented achieves speedups between log2N and (N+log2N)/2 where N is the number of processors in the parallel processor. Experimental results are presented on three versions of the basic method: the static, dynamic balanced, and dynamic unbalanced parallel-simulated-annealing algorithms View full abstract»

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  • Random testability analysis: comparing and evaluating existing approaches

    Publication Year: 1988 , Page(s): 70 - 73
    Cited by:  Papers (5)
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    The authors present a comparative approach to some testability analysis methods for application to VLSI devices. Using a common framework of implementations and test cases, they compared the results between analysis methods and with those provided by fault simulation or exact calculation where possible. The methods dealt with are the weighted averaging algorithm, COP, the cutting algorithm, Stafan, and Predict View full abstract»

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  • Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor

    Publication Year: 1988 , Page(s): 110 - 113
    Cited by:  Papers (3)  |  Patents (2)
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    The RPM40 32-bit CMOS microprocessor system and its initial architectural design tradeoffs are presented. The system is based around two custom VLSI chips, a CPU and an FPU, and has demonstrated programs operating at a 40-MIPS (million-instruction-per-second) peak rate for CPU integer operations. This peak rate is achieved when the CPU pipeline is full, without NOPS, and ignoring cache misses. The peak rate is achieved for many segments of code by careful reorganization of instructions View full abstract»

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  • Set-associative dynamic random access memory

    Publication Year: 1988 , Page(s): 478 - 483
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    Static-column dynamic RAMs (random-access memories) offer fast access to successive locations within a single row, a fact which has been used in their implementation in fast cacheless memory systems. Such caches are necessarily nonassociative (direct-mapped), limiting their performance relative to set-associative caches of similar total capacity. The authors describe an architecture for dynamic RAM chips which circumvents this limitation by providing several alternative static row buffers on each chip. Cacheless memory systems utilizing these devices are able to achieve the performance characteristics of relatively expensive set-associative cached memories using only economical high-density RAM parts. Simulation results on set-associate dynamic RAMs (SADRAMs) are presented and some plausible roles for SADRAMs in various architectural contexts are noted View full abstract»

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  • RISC architecture of the M88000

    Publication Year: 1988 , Page(s): 370 - 373
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    The 88000 processor family is one of the RISC (reduced-instruction-set computer) microcomputers that integrate the integer execution unit, the floating-point unit, the instruction fetch pipelines, and a data memory unit interface onto a single device. There are many supporting structures, such as advance branch target address calculation, dedicated units for memory address calculation, and bit field shifters to increase system performance. The 88000 device is structured such that each unit can perform concurrently, i.e. floating-point, integer, and data access instructions can all be being executed simultaneously while other instructions are being fetched. The author examines the 88000 machine to see how computing performance is gained through architectural enhancements View full abstract»

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