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Proceedings 1988 IEEE International Conference on Computer Design: VLSI

3-5 Oct. 1988

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Displaying Results 1 - 25 of 125
  • Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '88 (Cat. No.88CH2643-5)

    Publication Year: 1988, Page(s): 0_1
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    Freely Available from IEEE
  • Estimation of area and performance overheads for testable VLSI circuits

    Publication Year: 1988, Page(s):402 - 407
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochasti... View full abstract»

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  • Design of a high-speed arithmetic datapath

    Publication Year: 1988, Page(s):214 - 215
    Cited by:  Papers (8)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    This paper presents the implementation of a 64/32 bit floating-point datapath circuit (WTL3×64). This high-speed CMOS circuit integrates a 2 Kbit six-port register file, an independent 64/32-bit alu, a multiplier, and a divide/square-root unit for IEEE binary floating-point format numbers. It is fabricated using a 1.2 micron two-layer-metal CMOS technology. Operating at 60 ns cycle time, the... View full abstract»

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  • The KARL/KARATE system-integrating functional test development into a CAD environment for VLSI

    Publication Year: 1988, Page(s):209 - 212
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    KARATE is a system for testability analysis and automatic test pattern generation. It is embedded in the KARL design environment. Like the KARL environment, KARATE works on hardware descriptions at RT, gate, and switch level. A comfortable, interactive user interface makes the process of test-pattern generation transparent to the user. Badly controllable or badly observable hardware components or ... View full abstract»

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  • SID: synthesis of integral design

    Publication Year: 1988, Page(s):204 - 208
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The author describes the SID program, a knowledge-based expert system used for the synthesis of logic designs. A system architecture is presented with several major contributions: synthesis is performed on heterogeneous sets of logic elements in their natural physical partitions. Logic design database and rule language are customized to give rules complete decision and transformation capabilities ... View full abstract»

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  • ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovations

    Publication Year: 1988, Page(s):611 - 614
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    The author describes how IBM's most powerful system achieved significant growth through a balance of technology use and systems design. Selective use of a novel advanced transistor technology combined with innovative processor-design techniques solved many system design limitations. The author examines several system design problems and the solutions. He describes how a broad spectrum of systems a... View full abstract»

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  • Reconfiguration strategies in VLSI processor arrays

    Publication Year: 1988, Page(s):418 - 421
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Reconfiguration strategies in VLSI processor arrays have been advocated in the recent literature as a means of achieving higher production yield and higher reliability. The authors present reconfiguration techniques for rectangular arrays that are generalizations of the Diogenes approach proposed earlier by A.L. Rosenberg (1983). These techniques overcome many of the limitations of the earlier Dio... View full abstract»

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  • Direct synthesis of mapping circuits

    Publication Year: 1988, Page(s):200 - 203
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    In the context of mapping-based methods for multilevel circuit synthesis, the authors propose a method, called the direct implementation procedure (DIP), to synthesize combinational functions. An algebra is defined in which a set of mappings together with a parallel composition operation can produce arbitrary mappings. The resulting mappings can be easily implemented as macrocells. The DIP procedu... View full abstract»

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  • Extension of a transistor level digital timing simulator to include first order analog behavior

    Publication Year: 1988, Page(s):116 - 119
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The simulator is built on the second-generation MOTIS mixed-mode simulator to accommodate simulation for analog circuits. It uses circuit-simulation techniques for the analog portions of the chip, and timing and logic simulation techniques for the digital portions. The simulator can be used for overall design verification of a chip at the transistor level View full abstract»

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  • A rule based logic reorganization system LORES/EX

    Publication Year: 1988, Page(s):262 - 266
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors describe a rule-based logic reorganization system LORES/EX, which transforms an existing logic circuit into one that is dependent on other technology. The system can be not only flexibly adjustable to technology changes, but also has several special features as follows: (1) introduction of the circuit standardization rules makes the size of the rule base much smaller, and makes the des... View full abstract»

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  • On fault tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

    Publication Year: 1988, Page(s):554 - 559
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The design of fault-tolerant array structures from non-fault-tolerant array structures is studied. It is shown how hardware redundancy can be used in existing structures to make them capable of withstanding the failure of some of the array elements. Then distributed fault-tolerance schemes are introduced for the diagnosis of the fault elements, reconfiguration, and recovery of the array after fail... View full abstract»

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  • Verifiable and executable theories of design for synthesizing correct hardware

    Publication Year: 1988, Page(s):604 - 610
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Formally verified hardware synthesis functions have been developed and implemented using high-order logic, automatic theorem provers, and declarative languages. The synthesis functions, which take the form of equivalence-preserving transformations, enable implementations to be related to their specifications in a formally verified manner. As shown by the theory of design for array multipliers, ver... View full abstract»

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  • CESAR-A programmable high performance systolic array processor

    Publication Year: 1988, Page(s):414 - 417
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The authors describe the architecture and implementation of the CESAR computer system. The computing unit in CESAR has from one to four programmable systolic arrays working strictly in parallel, representing a SIMD (single-instruction multiple-data) structure. Each array consists of 128 custom-designed processing elements individually programmable for performing bit-serial operations on 32-bit dat... View full abstract»

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  • Representation of control and timing behavior with applications to interface synthesis

    Publication Year: 1988, Page(s):382 - 387
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than som... View full abstract»

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  • Processor design using path programmable logic

    Publication Year: 1988, Page(s):196 - 199
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Path programmable logic (PPL) is a VLSI design methodology that is very efficient in the implementation of systems consisting of random logic, counters, and finite-state machines. Previous designs have shown that PPL does not efficiently allow the implementation of bus-oriented designs, such as microprocessors, arithmetic processors, and DSP (digital signal processor) chips. The authors present so... View full abstract»

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  • Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor

    Publication Year: 1988, Page(s):110 - 113
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The RPM40 32-bit CMOS microprocessor system and its initial architectural design tradeoffs are presented. The system is based around two custom VLSI chips, a CPU and an FPU, and has demonstrated programs operating at a 40-MIPS (million-instruction-per-second) peak rate for CPU integer operations. This peak rate is achieved when the CPU pipeline is full, without NOPS, and ignoring cache misses. The... View full abstract»

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  • Mapping properties of multi-level logic synthesis operations

    Publication Year: 1988, Page(s):257 - 261
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    It was found that synthesis operations like kernel extraction-intersection and phase assignment have excellent mapping properties in the synthesis of multilevel Boolean networks when a symmetric (dual) target library of standard cells is used. This was made possible by DIRMAP, a simple translator of the optimized and properly decomposed set of Boolean functions, which produces 4 to 12% better area... View full abstract»

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  • Stop criteria in simulated annealing

    Publication Year: 1988, Page(s):549 - 552
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The authors propose stopping criteria based on statistics collected during the annealing. In contrast to conventional stop criteria, the proposed criteria do not depend on the move set. Specifically, formulae are presented for detecting that an adequate final temperature has been reached. The arguments of the formulae are obtained by observing the behavior of the variance of the score for the inst... View full abstract»

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  • A methodology for the control and custom VLSI implementation of large-scale Clos networks

    Publication Year: 1988, Page(s):472 - 477
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A control algorithm is developed and implemented for a three-stage Clos network which results in using a multiple-chip approach. The system will be nonblocking in the strict sense and completely self-routing, i.e. the controller for the network will reside in the network and not in a separate computer that runs a program that controls switches to the interconnect array. Intermodule communication r... View full abstract»

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  • Proof and synthesis

    Publication Year: 1988, Page(s):600 - 603
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The authors argue that the next generation of computer-aided design (CAD) tools will represent and manipulate behavior. Behavioral tools are necessary to provide fast reliable design of complex systems. An approach to high-level synthesis is described which has grown out of formal verification using mathematical logic. It is shown that a general-purpose proof strategy combined with simple design r... View full abstract»

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  • A novel VLSI architecture for the real-time implementation of 2-D signal processing systems

    Publication Year: 1988, Page(s):582 - 585
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The authors present a high-performance VLSI architecture for two-dimensional (2-D) digital signal processing applications. The architecture uses a specially designed digital signal processor (DSP) as a node in a multiprocessor system for real-time or near-real-time 2-D signal processing. The DSP is custom-designed and has a throughput of two multiplications and three additions in a single cycle. I... View full abstract»

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  • Multi-chip packaging for high performance systems

    Publication Year: 1988, Page(s):76 - 81
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Multichip module (MCM) substrate, component assembly, and cooling technologies have been developed and demonstrated on several vehicles that include a 4-Kbyte RAM module operating at above 100-MHz clock frequency. An optimum MCM may consist of a set of composite layers of a multi-layer thin film polyimide structure over a multilayer ceramic substrate with a high pin density. The MCM technology pro... View full abstract»

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  • A modular scan-based testability system

    Publication Year: 1988, Page(s):408 - 412
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The authors present a scan-based testability system that is an integral part of the cell-based design system at Microelectronics Center of North Carolina. The basic system consists of five modules: a scan-based audit to verify compliance with scan-based rules, a testability assessment module that projects fault coverage before any patterns are applied, a fast fault simulator that grades random and... View full abstract»

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  • Synthesis from VHDL

    Publication Year: 1988, Page(s):378 - 381
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The VHDL Synthesis System (VSS) uses VHDL dataflow or behavioral descriptions as input and outputs a structural description of generic components. This structural description is converted into a schematic and captured by the microarchitecture and logic optimization system for technology mapping and constraint-driven optimization. VSS allows a designer to modify the compiled design by changing the ... View full abstract»

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  • An octagonal geometry compactor

    Publication Year: 1988, Page(s):190 - 193
    Cited by:  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Layout compactors have been widely adopted by symbolic layout systems to compact circuit layout. A common limitation among current state-of-the-art compactors is that they can only compact orthogonal geometries. The author describes a one-dimensional compactor that can compact arbitrary octagonal geometries. The compactor is based on the constraint graph approach. The octagonal geometry compactor ... View full abstract»

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