International Test Conference 1988 Proceeding@m_New Frontiers in Testing

12-14 Sept. 1988

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Displaying Results 1 - 25 of 134
  • Concurrent control of multiple BIT structures

    Publication Year: 1988, Page(s):431 - 442
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (860 KB)

    A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogramme... View full abstract»

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  • International Test Conference 1988 Proceedings - New Frontiers in Testing (Cat. No.88CH2610-4)

    Publication Year: 1988
    Request permission for commercial reuse | |PDF file iconPDF (24 KB)
    Freely Available from IEEE
  • Elimination of incoming test based upon in-process failure and repair costs

    Publication Year: 1988, Page(s):308 - 313
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (297 KB)

    An economic model was developed that challenges traditional statistical quality-control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM (parts per million) quality level and the lot-to-lot stability. When incoming quality levels fall to below 100 PPM, the model can be used to reevaluate conventional test strategies in high volume manufacturing ope... View full abstract»

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  • Fault simulation and test pattern generation at the multiple-valued switch level

    Publication Year: 1988, Page(s):94 - 101
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB)

    A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors' main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults whic... View full abstract»

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  • Automatic location of IC design errors using an E-beam system

    Publication Year: 1988, Page(s):898 - 907
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (644 KB)

    The ADVICE system discussed is an enhanced CAD (computer-aided design) linked E-beam tester to locate automatically design errors on custom VLSI devices. The goal is met by building a set of procedures to drive the interactive electron-beam debugging (EBD) system according to the strategies devised by the algorithms based on fault dictionary/hierarchical probing algorithm mixed search View full abstract»

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  • A parallel algorithm for fault simulation on the Connection Machine

    Publication Year: 1988, Page(s):89 - 93
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    A fast algorithm for fault simulation, using data-level parallelism, is presented for the Connection Machine. The algorithm is of the parallel pattern single-fault-propagation type. An implementation in C language has been completed and results are presented View full abstract»

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  • Designs for diagnosability and reliability in VLSI systems

    Publication Year: 1988, Page(s):888 - 897
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (472 KB)

    Novel concepts of designs for diagnosability and reliability are defined and developed. A diagnosable design of VLSI system is presented, in which fault isolation is realized by minimal additional hardware instead of traditional software diagnostic procedures such that the computation space and time for fault isolation are saved. The presented fault-tolerant design uses online fault detection and ... View full abstract»

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  • Semiconductor perspective on test standards

    Publication Year: 1988, Page(s):197 - 198
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (152 KB)

    Developing testable products cost-effectively requires that a standard, such as JTAG and the IEEE P-1149, be adopted. The system developer and semiconductor manufacturer need to share in this development effort to accelerate adoption. The system developer must gain a better understanding of the total cost of ownership for a testable vs. a nontestable product and the semiconductor manufacturer must... View full abstract»

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  • On benchmarking digital testing systems

    Publication Year: 1988
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (112 KB)

    An approach to quantify the digital testing system (DTS) attributes is presented. The quantification will help in determining criteria according to which benchmark circuits are selected. Two main parameters that can be used in the comparison are the speed of operation and memory requirements. Attempts are made to relate each of these two parameters to different attributes of the DTS. Experiments w... View full abstract»

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  • A high-resolution waveform analysis tool

    Publication Year: 1988, Page(s):547 - 550
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (244 KB)

    A system is described for very-high-resolution measurement, statistical analysis, and graphical display of waveforms appearing on a VLSI device. Capabilities include superimposing graphs of waveforms resulting from differing test conditions or from different pins. Measurement is done by averaging the results of multiple trials. The measurement device has a resolution of 3 ps, accuracy of 100 ps, a... View full abstract»

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  • Hierarchical test generation using precomputed testsd for modules

    Publication Year: 1988, Page(s):221 - 229
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (700 KB)

    A novel test-generation technique for large circuits with high fault-coverage requirements is described. Circuit modules and signals are represented at a high descriptive level. Test data for modules are represented by predefined stimulus/response packages which are processed symbolically using techniques derived from artificial intelligence. Since many test vectors are processed simultaneously, a... View full abstract»

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  • Trouble-shooting: a key to process improvement

    Publication Year: 1988, Page(s):796 - 803
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (668 KB)

    The authors present a problem-solving methodology that consists of four basic steps-collecting data, identifying problems, uncovering root causes, and taking action. With the recent advance in computer-integrated manufacturing (CIM), endeavors to improve the process have been greatly eased by the deployment of such systems as ILIAD and MPCS. It is described how some of the tools provided by these ... View full abstract»

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  • Synthesis and optimization procedures for fully and easily testable sequential machines

    Publication Year: 1988, Page(s):621 - 630
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (860 KB)

    A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be ... View full abstract»

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  • Detection of control flow errors using signature and checking instructions

    Publication Year: 1988, Page(s):81 - 88
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (640 KB)

    An approach is presented to the online detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are embedded into the program memory using the monitored processor instructions. Compared with existing techniques, the presented approach is universal and can be easily implemented using... View full abstract»

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  • System level fault dictionary generation

    Publication Year: 1988, Page(s):884 - 887
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (212 KB)

    A fault dictionary generation (FDG) system, which generates a system-level fault dictionary automatically from structural description of computer system hardware, was developed and applied to a large scale computer system. Built-in diagnosis (BID), which is effective in detecting and locating a fault, is described briefly. The mechanism to generate a fault dictionary, based on BID capability, is d... View full abstract»

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  • Boundary scan-the ATE vendors' view

    Publication Year: 1988, Page(s):195 - 196
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (156 KB)

    The author discusses boundary scan which incorporates the use of special components which are linked together to allow access to the internal nodes of a printed circuit board (PCB) without the need to make physical contact through a bed of nails fixture. Boundary scan is one solution for the process verification of highly integrated digital boards where node access is impossible because of extensi... View full abstract»

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  • An expert test program generation system for per-pin testers

    Publication Year: 1988, Page(s):665 - 668
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (252 KB)

    The development is discussed of a rules-based automatic test-program generator (ATPG) that integrates IBM's CAD (computer-aided design) system with a per-pin tester. The authors describe the versatility of the ATPG that gleans test patterns and the logic model from the CAD system, merges produce technology characteristics and generates a complete test program that verifies the electrical, function... View full abstract»

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  • Designing state machines for testability

    Publication Year: 1988
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (96 KB)

    The current generation of programmable logic devices provides circuit designers with options in high-speed controller design. These devices fill the performance gap between low-cost integrated microcontrollers and more expensive ASIC (application-specific) solutions. A technique of designing state machines that are easily testable is described. The design technique presented utilizes characteristi... View full abstract»

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  • GaAs driver and sensor for a high speed system

    Publication Year: 1988, Page(s):13 - 22
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (564 KB)

    The circuitry of a GaAs driver/sensor device was presented. The specific features that it possesses and the design issues were discussed. The device was prototyped using MMIC (monolithic microwave integrated circuit) techniques and packaged in hybrid form. Experimental results indicated that its performance well exceeded the designated goal at 100 MHz. After intensive SPICE simulations confirmed t... View full abstract»

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  • Some new techniques in waveshape capture and analysis

    Publication Year: 1988, Page(s):537 - 546
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (588 KB)

    The techniques implemented in WAVESCAN have resulted in a waveshape capture and analysis tool that is fast and easy to use, and which at the same time provides the user with a more accurate and comprehensive view of real-time signal behavior at the pins of a VLSI device under test. A lack of published specifications and benchmark data on other waveshape software makes rigorous comparison impossibl... View full abstract»

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  • Practice and theory [IC testing]

    Publication Year: 1988, Page(s):203 - 204
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (180 KB)

    The author addresses the question of knowledge transfer between industry and academy in the area of integrated-circuit (IC) testing. He first examines the movement of theory from academia to industrial practice, finding two problems: designers are evaluated on meeting deadlines not on testability; and most designers do not know how to ensure testability in a systematic fashion. The solutions are t... View full abstract»

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  • Partial hardware partitioning: a new pseudo-exhaustive test implementation

    Publication Year: 1988
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (84 KB)

    A pseudoexhaustive-test implementation technique is presented which combines the advantages of hardware partitioning and sensitized partitioning, offering lower hardware overhead than hardware partitioning, and lower test-set generation complexity and higher fault coverage than sensitized partitioning View full abstract»

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  • Design for testability of mixed signal integrated circuits

    Publication Year: 1988, Page(s):823 - 828
    Cited by:  Papers (73)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integra... View full abstract»

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  • Stuck-open and transition fault testing in CMOS complex gates

    Publication Year: 1988, Page(s):688 - 694
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB)

    A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used t... View full abstract»

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  • Expert system for the functional test program generation of digital electronic circuit boards

    Publication Year: 1988, Page(s):209 - 220
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (948 KB)

    CAD (computer-aided design)-generated component and interconnection listings are utilized to recreate a circuit design in the form of an associated network. This is stored within an expert system's database and enables a powerful search algorithm, under the guidance of testability formulation rules, to explore the circuit. The algorithm interacts with these device models and register-transfer-logi... View full abstract»

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