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International Test Conference 1988 Proceeding@m_New Frontiers in Testing

12-14 Sept. 1988

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Displaying Results 1 - 25 of 134
  • Concurrent control of multiple BIT structures

    Publication Year: 1988, Page(s):431 - 442
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogramme... View full abstract»

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  • International Test Conference 1988 Proceedings - New Frontiers in Testing (Cat. No.88CH2610-4)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (24 KB)
    Freely Available from IEEE
  • Elimination of incoming test based upon in-process failure and repair costs

    Publication Year: 1988, Page(s):308 - 313
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB)

    An economic model was developed that challenges traditional statistical quality-control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM (parts per million) quality level and the lot-to-lot stability. When incoming quality levels fall to below 100 PPM, the model can be used to reevaluate conventional test strategies in high volume manufacturing ope... View full abstract»

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  • Switch-level concurrent fault simulation based on a general purpose list traversal mechanism

    Publication Year: 1988, Page(s):574 - 581
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A general-purpose traversal mechanism is described which is used to perform concurrent simulation for complex devices. This traversal mechanism performs all list handling necessary for an accurate and efficient concurrent simulation at a complexity level much higher than that of the gate level. The work on this general-purpose traversal mechanism project has been done within the DECSIM logic simul... View full abstract»

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  • Fault bundling: reducing machine evaluation activity in hierarchical concurrent fault simulation

    Publication Year: 1988, Page(s):569 - 573
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A method of bundling error data is proposed which should significantly reduce the amount of explicit functional evaluation required for hierarchical concurrent simulation. The bundling operation is carried out at run time, and so is different from but complementary to approaches such as WRAP, which compress unnecessary or uninteresting portions of circuit hierarchy. The technique is exact; it does... View full abstract»

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  • Optimal use of timing resources: a crucial step in test program generation

    Publication Year: 1988, Page(s):460 - 465
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    A modified timing set priority strategy and a lookahead register-replacement algorithm is presented for automatic test program generation. These methodologies are introduced to satisfy the testing requirements in complex VLSI chips, and are made possible by the increasing timing flexibility of modern ATE (automatic test equipment). It is shown that by applying optimization algorithms in allocating... View full abstract»

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  • Error detection with latency in sequential circuits

    Publication Year: 1988, Page(s):926 - 933
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with l... View full abstract»

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  • PGTOOL: an automatic interactive program generation tool for testing new-generation memory devices

    Publication Year: 1988, Page(s):559 - 568
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    PGTOOL generates pattern and timing source files for device testing on the 1937 memory test system. Using macro files that describe the main sequence and testing specifications for patterns and timing, PGTOOL communicates this information in pictures, making programming faster, easier, and less prone to errors. The program combines automatic code generation with a graphics interface, resulting in ... View full abstract»

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  • CAD tools for supporting system design for testability

    Publication Year: 1988
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed t... View full abstract»

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  • Very high density probing

    Publication Year: 1988, Page(s):608 - 614
    Cited by:  Papers (6)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    A discussion is presented on some of the problems encountered with probing at the wafer level and how this probe card technology helps to overcome those problems. Advancements needed in probe card technology include smaller pitches, faster speeds, bumped pads, internal and multidie probing. With the density of the die increasing, the pitch between pads on the die is being reduced. A pitch of 4 mil... View full abstract»

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  • Defining a standard for fault simulator evaluation

    Publication Year: 1988
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    An acceptable standard is developed for relating fault simulator results from different simulators. Each simulator should verify the good circuit and evaluate the effectiveness of the generated test patterns (fault coverage). A hypothetical standard set of characteristics are proposed and each of the simulators are redefined in terms of the standard. These recommendations for evaluating these faul... View full abstract»

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  • A high level approach to integrating design and test

    Publication Year: 1988, Page(s):452 - 459
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The STL simulation and test language described provides a high-level approach to the problem of integrating design and test. This common programming language and environment can be used by both designers and test engineers to develop functional tests for both simulators and testers. The STL programming environment can be effectively used to increase the productivity of both designers and test engi... View full abstract»

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  • Integrated pin electronics for a VLSI test system

    Publication Year: 1988, Page(s):23 - 27
    Cited by:  Papers (7)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology View full abstract»

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  • Robust tests for parity trees

    Publication Year: 1988, Page(s):680 - 687
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Tests to detect line stuck-at and transistor stuck-open faults in CMOS binary parity trees are considered. The main objective was to derive bounds on test sequences and test sequences that detect all single faults, even in the presence of circuit delays. It is shown that the desired robustness of test requires tests whose lengths are proportional to the depth of the trees under test, in contrast t... View full abstract»

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  • Continuous signature monitoring: efficient concurrent-detection of processor control errors

    Publication Year: 1988, Page(s):914 - 925
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    Concurrent detection of processor control errors using signatured programs is discussed. The approach, called continuous signature monitoring (CSM), makes significant advances beyond the existing signature-monitoring techniques. For typical programs, CSM decreased average error-detection latency by as much as eight times, down to 1.2 to 1.6 program memory cycles. Memory overhead for storing signat... View full abstract»

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  • Functional test program generation through interactive graphics

    Publication Year: 1988, Page(s):551 - 558
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A methodology and the implementation are described of a graphical waveform editor which is used to create functional test programs on an engineering workstation. The system has been implemented such that timing and test patterns can be created or customized for different target testers utilizing diverse timing technologies. The graphical waveform editor is described in the context of an integrated... View full abstract»

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  • Scan diagnostic strategy for the series 10000 PRISM workstation

    Publication Year: 1988, Page(s):987 - 992
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The Series 10000 PRISM workstation has been designed to be testable using scan path techniques. An overview of the scan architecture at the chip and system levels shows the basis on which a diagnostic strategy was developed. These strategies were used to achieve diagnostics goals of high fault coverage and component-level fault isolation. A unique fault-isolation method is described which is based... View full abstract»

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  • Digital testing theory and practice

    Publication Year: 1988, Page(s):205 - 206
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    Digital testing is an emerging interdisciplinary branch of engineering. A solid foundation in the field requires good knowledge of calculus and discrete mathematics, and an awareness of the practical considerations encountered in actual testing of the digital systems. The balance of theory and practice within a digital testing course taught by the author is examined, and it is shown to be a functi... View full abstract»

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  • A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability

    Publication Year: 1988, Page(s):329 - 342
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    A coding theory framework is developed for analysis and synthesis of compression techniques in the built-in self test (BIST) environment. Using this framework, exact expressions are derived for the linear feedback shift register aliasing probability. These are shown to be more accurate than earlier ones. Also shown is that there exist compression techniques for which the aliasing probability can b... View full abstract»

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  • Membrane probe card technology (the future for higher performance wafer test)

    Publication Year: 1988, Page(s):601 - 607
    Cited by:  Papers (17)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A probe card technology is described that addresses the needs of testing VLSI devices at the wafer level. This technology offers the ability to test high-pin count devices at operating speed with the same performance as obtained in package test. The design and performance characteristics of two implementations are summarized and the results of several applications are reviewed View full abstract»

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  • Test head design using electrooptic receivers and GaAs pin electronics for a gigahertz production test system

    Publication Year: 1988, Page(s):700 - 709
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A test head subsystem providing ultrahigh-speed digital signal paths to a device under test is introduced and described. The test head houses liquid-cooled GaAs pin electronics capable of NRZ (non-return-to-zero) data rates up to 1.2 Gb/s. A novel test system receiver scheme utilizing an electrooptic (laser) measurement method is described which captures pin information by connecting the device un... View full abstract»

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  • Dual port static RAM testing

    Publication Year: 1988, Page(s):362 - 368
    Cited by:  Papers (26)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The basics are presented of a test methodology used for dual-port static RAMs (random-access memories). The fundamental problem in testing dual-port static RAMs is how to address the entire array from both sides individually. Any memory tester with dual pattern generators and dual timing systems would suffice, but most existing memory testers were designed and built before dual-port static RAMs we... View full abstract»

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  • An incomplete scan design approach to test generation for sequential machines

    Publication Year: 1988, Page(s):730 - 734
    Cited by:  Papers (50)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    An incomplete scan design approach to sequential test generation is presented. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable ... View full abstract»

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  • Testability features of a 32 kbps ADPCM transcoder

    Publication Year: 1988, Page(s):161 - 171
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    Motorola's MC 145532 ADPCM (adaptive digital pulse-code-modulation) transcoder described is a 16-pin CMOS VLSI application specific digital signal processor (DSP) that implements in full-duplex mode the ANSI (T1.301-1987) standard algorithm for 32-kb/s ADPCM. The application is illustrated of structured test techniques, such as scan path and signature analysis, which are used to enhance the testab... View full abstract»

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  • Partial hardware partitioning: a new pseudo-exhaustive test implementation

    Publication Year: 1988
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A pseudoexhaustive-test implementation technique is presented which combines the advantages of hardware partitioning and sensitized partitioning, offering lower hardware overhead than hardware partitioning, and lower test-set generation complexity and higher fault coverage than sensitized partitioning View full abstract»

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