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International Test Conference 1988 Proceeding@m_New Frontiers in Testing

12-14 Sept. 1988

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Displaying Results 1 - 25 of 134
  • Concurrent control of multiple BIT structures

    Publication Year: 1988, Page(s):431 - 442
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogramme... View full abstract»

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  • International Test Conference 1988 Proceedings - New Frontiers in Testing (Cat. No.88CH2610-4)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (24 KB)
    Freely Available from IEEE
  • Elimination of incoming test based upon in-process failure and repair costs

    Publication Year: 1988, Page(s):308 - 313
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB)

    An economic model was developed that challenges traditional statistical quality-control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM (parts per million) quality level and the lot-to-lot stability. When incoming quality levels fall to below 100 PPM, the model can be used to reevaluate conventional test strategies in high volume manufacturing ope... View full abstract»

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  • A knowledge representation scheme for DFT

    Publication Year: 1988, Page(s):631 - 641
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    The knowledge-based approach to design for test (DFT) and test generation is discussed which depends heavily upon a storehouse of knowledge about DFT techniques and their application. The knowledge representation requirements of this knowledge-based approach are analyzed. An integrated knowledge representation scheme called KRAFT which addresses the representation requirements is presented in deta... View full abstract»

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  • Synthesis and optimization procedures for fully and easily testable sequential machines

    Publication Year: 1988, Page(s):621 - 630
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be ... View full abstract»

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  • New automated prober support for high pincount test heads

    Publication Year: 1988, Page(s):615 - 620
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Automatic best-fit tip-to-pad alignment and skewed chip probing based on high-speed image processing is described. A complete solution is presented to automate and optimize the probe set up. It can be implemented as operator assist or as total automation, depending on the status of the local system. It is concluded that high-speed image processing techniques should also be able to keep pace with t... View full abstract»

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  • Techniques for user testing of the 68882

    Publication Year: 1988, Page(s):942 - 947
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The steps required to develop a test program for the Motorola 68882 floating-point coprocessor, are documented, using only functional techniques. The resulting test program for the 68882 executes 550000 clock cycles and tests 2700 instructions. The functional test method, LEAD, is ideal for the user, since the program generates vectors directly from assembly language and test the 68882 just as it ... View full abstract»

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  • Microprocessor testing by instruction sequences derived from random patterns

    Publication Year: 1988, Page(s):73 - 80
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A novel technique for testing a microprocessor by instruction sequences generated with an LFSR (linear-feedback shift register) is presented. By translating pseudorandom patterns into the mnemonic code an efficient test pattern generator can be constructed in a straightforward way. It is shown that the resulting instruction sequence is equivalent to a functional test but less expensive. Subsequent... View full abstract»

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  • Very high density probing

    Publication Year: 1988, Page(s):608 - 614
    Cited by:  Papers (6)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    A discussion is presented on some of the problems encountered with probing at the wafer level and how this probe card technology helps to overcome those problems. Advancements needed in probe card technology include smaller pitches, faster speeds, bumped pads, internal and multidie probing. With the density of the die increasing, the pitch between pads on the die is being reduced. A pitch of 4 mil... View full abstract»

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  • In-circuit test fixture

    Publication Year: 1988, Page(s):391 - 400
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Two failure modes are identified for the conventional in-circuit fixture. The fixture is compared with a conventional fixture and is found to be superior. The fixture provides a coaxial-like raceway to propagate signals. Crosstalk and mismatch are greatly reduced View full abstract»

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  • On benchmarking digital testing systems

    Publication Year: 1988
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    An approach to quantify the digital testing system (DTS) attributes is presented. The quantification will help in determining criteria according to which benchmark circuits are selected. Two main parameters that can be used in the comparison are the speed of operation and memory requirements. Attempts are made to relate each of these two parameters to different attributes of the DTS. Experiments w... View full abstract»

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  • Concurrent off-phase built-in self-test of dormant logic

    Publication Year: 1988, Page(s):934 - 941
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Concurrent off-phase built-in self-test is described, which permits the operation of built-in self-test hardware designed for offline testing concurrently with normal system operations. It takes advantage of the logic dormancy characteristic of designs which use two-phase clocking. This method provides online detection for permanent faults and can be used in conjunction with a time-redundant concu... View full abstract»

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  • Design for testability of a 32-bit microprocessor-the TX1

    Publication Year: 1988, Page(s):172 - 182
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described. Clear testing strategies were developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is highly enhanced by the use of the bus structure or microinstruction set of the TX1. Fault coverage ... View full abstract»

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  • Switch-level concurrent fault simulation based on a general purpose list traversal mechanism

    Publication Year: 1988, Page(s):574 - 581
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A general-purpose traversal mechanism is described which is used to perform concurrent simulation for complex devices. This traversal mechanism performs all list handling necessary for an accurate and efficient concurrent simulation at a complexity level much higher than that of the gate level. The work on this general-purpose traversal mechanism project has been done within the DECSIM logic simul... View full abstract»

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  • On multiple fault coverage and aliasing probability measures

    Publication Year: 1988, Page(s):314 - 321
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    A comparative study is presented of different methods of calculating multiple fault coverage and aliasing probability measures. The objectives are to describe the ways that these ratios are defined to give them a physical interpretation, and to separate the discussion of how to define the measure from how the measure might be actually obtained or calculated. The interpretation, accuracy, and appli... View full abstract»

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  • Designs for diagnosability and reliability in VLSI systems

    Publication Year: 1988, Page(s):888 - 897
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Novel concepts of designs for diagnosability and reliability are defined and developed. A diagnosable design of VLSI system is presented, in which fault isolation is realized by minimal additional hardware instead of traditional software diagnostic procedures such that the computation space and time for fault isolation are saved. The presented fault-tolerant design uses online fault detection and ... View full abstract»

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  • Testing and diagnosis of interconnects using boundary scan architecture

    Publication Year: 1988, Page(s):126 - 137
    Cited by:  Papers (102)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed... View full abstract»

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  • Analysis of experimental results on functional testing and diagnosis of complex circuits

    Publication Year: 1988, Page(s):64 - 72
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A number of functional-level test approaches for microprocessors have been proposed. The GAPT approach, presented here, is a pragmatic one, but it is supported by a set of tools and experimental results. The authors describe the GAPT approach in detail. They draw tentative conclusions with respect to the effectiveness and scope of these functional test generation methods View full abstract»

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  • Expert system for the functional test program generation of digital electronic circuit boards

    Publication Year: 1988, Page(s):209 - 220
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    CAD (computer-aided design)-generated component and interconnection listings are utilized to recreate a circuit design in the form of an associated network. This is stored within an expert system's database and enables a powerful search algorithm, under the guidance of testability formulation rules, to explore the circuit. The algorithm interacts with these device models and register-transfer-logi... View full abstract»

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  • Membrane probe card technology (the future for higher performance wafer test)

    Publication Year: 1988, Page(s):601 - 607
    Cited by:  Papers (17)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A probe card technology is described that addresses the needs of testing VLSI devices at the wafer level. This technology offers the ability to test high-pin count devices at operating speed with the same performance as obtained in package test. The design and performance characteristics of two implementations are summarized and the results of several applications are reviewed View full abstract»

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  • An advanced data compaction approach for test-during burn-in

    Publication Year: 1988, Page(s):381 - 390
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    A novel burn-in system approach, using data compaction, test generation tools, and a flexible, general-purpose test system architecture is described. The approach offers true output monitoring of multioutput devices, featuring monitoring capabilities of 1-2000 test points per burn-in board. The approach is also well suited for testing of analog parts during burn-in, or may find usage for individua... View full abstract»

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  • Designing state machines for testability

    Publication Year: 1988
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The current generation of programmable logic devices provides circuit designers with options in high-speed controller design. These devices fill the performance gap between low-cost integrated microcontrollers and more expensive ASIC (application-specific) solutions. A technique of designing state machines that are easily testable is described. The design technique presented utilizes characteristi... View full abstract»

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  • Error detection with latency in sequential circuits

    Publication Year: 1988, Page(s):926 - 933
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with l... View full abstract»

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  • Testability features of a 32 kbps ADPCM transcoder

    Publication Year: 1988, Page(s):161 - 171
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    Motorola's MC 145532 ADPCM (adaptive digital pulse-code-modulation) transcoder described is a 16-pin CMOS VLSI application specific digital signal processor (DSP) that implements in full-duplex mode the ANSI (T1.301-1987) standard algorithm for 32-kb/s ADPCM. The application is illustrated of structured test techniques, such as scan path and signature analysis, which are used to enhance the testab... View full abstract»

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  • Predicting and obtaining high final test yields

    Publication Year: 1988, Page(s):804 - 815
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    A model is presented that accurately predicted final test yields following board test for over 75000 boards representing 33 board types. Enhanced in-circuit test commonly provided >95% final test yields. Included are power supplies, high-accuracy analog measurement instrument circuitry, digital controller boards of various sorts using microprocessors or custom devices, medical instrumentation c... View full abstract»

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