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Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE

Date 12-15 June 1988

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Displaying Results 1 - 25 of 101
  • 25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3)

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    Freely Available from IEEE
  • Automatic insertion of BIST hardware using VHDL

    Page(s): 9 - 15
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    A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.<> View full abstract»

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  • VLSI design synthesis with testability

    Page(s): 16 - 21
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    A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example has been used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST (built-in-self-testing) with different test schedules have been explored. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.<> View full abstract»

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  • A defect-tolerant and fully testable PLA

    Page(s): 22 - 27
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    The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.<> View full abstract»

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  • Experience with the VHDL environment

    Page(s): 28 - 33
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    The authors present their work in the use of the VHDL (VHSIC Hardware Development Language) environment on three different models of DEC VAX (1, 4, and 5.8 Mips (million instruction per second)). The work included the development of a number of VHDL models and sequences of input stimuli and the gathering of performance data from their execution. Even though the set of benchmarks is not in any way exhaustive, they represent typical applications, making it possible to derive performance models for predicting both time and memory requirements for VHDL modeling and simulation. It is shown that the performances of the VHDL environment on the three computers correlate perfectly with their Mips figures; thus the performance models developed can be normalized to a 1-Mips VAX machine.<> View full abstract»

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  • The role of VHDL in the MCC CAD system

    Page(s): 34 - 39
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    A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable Lisp functions, an elaborator for generating simulation models from complete design, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.<> View full abstract»

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  • Verification of VHDL designs using VAL

    Page(s): 48 - 53
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    VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL. An overview is given of design checking using VAL. VAL is described in detail and it is shown how VAL annotations are used to generate constraints on a VHDL simulation. A brief overview of the VAL transformer demonstrates the feasibility of the design. Some observations based on experience with VAL to date and areas for future work are considered.<> View full abstract»

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  • A module area estimator for VLSI layout

    Page(s): 54 - 59
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    An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<> View full abstract»

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  • Optimal aspect ratios of building blocks in VLSI

    Page(s): 66 - 71
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    A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.<> View full abstract»

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  • A method of delay fault test generation

    Page(s): 90 - 95
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    The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input. The authors extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at-tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.<> View full abstract»

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  • A notation for describing multiple views of VLSI circuits

    Page(s): 102 - 107
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    A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.<> View full abstract»

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  • A graphical hardware design language

    Page(s): 108 - 114
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    Gdl is a graphical hardware design language that separates design decisions into three interrelated but distinct domains: behavioral, structural, and physical. Specific language features are provided to represent a design in each of these domains. The process model for Gdl is described. Functional behavior is separated into distinct activities called 'processes' (autonomous control centers). The computations performed by a process are specified in its behavior graph. Processes may communicate with each other through ports where the channel between two ports may be an abstract logical link or may be a physical bus. Provisions are made for synchronization. Gdl is evaluated and suggestions are made for future research.<> View full abstract»

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  • A human machine interface for silicon compilation

    Page(s): 115 - 120
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    A description is given of a novel human-machine interface for use as a design environment for silicon compilation. It is important for a human machine interface to support a tool which realizes quick turn around time with little possibility of user errors. Designers should be able to work with little interference with their thinking process. To realize such a design environment, the authors have developed an LCD digitizer, and it has been demonstrated that this device can be a designer-friendly human-machine interface.<> View full abstract»

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  • Parallel placement on reduced array architecture

    Page(s): 121 - 127
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    The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal solutions for the smaller problems into a near-optimal solution for the original placement problem. The algorithm lends itself very naturally to a parallel realization, and maps nicely onto an SIMD (single-instruction, multiple data-stream) organization. Considerations such as cost-effectiveness and suitability to VLSI implementation led to the selection of the reduced array architecture as the target architecture for the placement accelerator.<> View full abstract»

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  • Mask verification on the Connection Machine

    Page(s): 134 - 140
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    Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. A discussion is presented of the design and implementation of algorithms for several essential primitives: generation of completely intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spacing violations. Performance results from experiments on a 16K-processor machine are presented. Speedups between 40 and 240 over a VAX 11/785 have been measured.<> View full abstract»

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  • On path selection in combinational logic circuits

    Page(s): 142 - 147
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    The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches.<> View full abstract»

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  • ATV: an abstract timing verifier

    Page(s): 154 - 159
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    A discussion is presented of implementation and extensions of an abstract timing verifier, and in particular, several novel operations and a novel algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to check a design for timing errors when the clock schedule is fixed and known, or to derive spacing constraints between clock edges when only the relative ordering of the clock edges is known. All algorithms are designed to operate on a wide variety of representation of time and delay.<> View full abstract»

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  • Parallel logic simulation on general purpose machines

    Page(s): 166 - 171
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    Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.<> View full abstract»

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  • Formal specification and verification of hardware: a comparative case study

    Page(s): 197 - 204
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    A report is presented on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. The strategy consists of working with incrementally harder test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device.<> View full abstract»

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  • Proving circuit correctness using formal comparison between expected and extracted behaviour

    Page(s): 205 - 210
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    A novel method is presented for verifying functionality in the design of VLSI circuits. The method fits naturally in a methodology based on a hardware description language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behavior from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to the HDL semantics. The authors define a process named formal analysis that permits to prove these properties without setting values to the programs inputs. Formal analysis is based on a canonical form of Boolean logic that is named typed Shannon's canonical form. They implemented this method in PRIAM, an efficient circuit prover now used by industrial CPU designers.<> View full abstract»

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  • Formal verification of the Sobel image processing chip

    Page(s): 211 - 217
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    An approach is described for hardware verification in the context of the authors' recent success in formally verifying the description of an image-processing chip. They demonstrate that their approach, which uses an implementation of an equational approach to theorem proving developed by D. Kapur and P. Narendran (1985), can be a viable alternative to simulation. In particular, they are able to take advantage of the recursive nature of many circuits, such as n-bit adders, and their techniques allow verification of sequential circuits. To the best of their knowledge this is the first time a complex sequential circuit which was not designed with formal verification specifically in mind has been verified. They describe the discovery of several design errors in the circuit description, detected during the verification attempt (the actual verification could only take place once these errors were removed).<> View full abstract»

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  • The IBM engineering verification engine

    Page(s): 218 - 224
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    A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An overview is given of the EVE architecture, hardware and software, and some current applications are described.<> View full abstract»

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  • Logic simulation system using simulation processor (SP)

    Page(s): 225 - 230
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    A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<> View full abstract»

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  • Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance

    Page(s): 231 - 236
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    A very-large-scale logic simulation engine called VELVET has been developed. VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and register-transfer level structure. VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. A description is given of how to realize such high performance. An algorithm is presented for vectorizing the simulation and performance.<> View full abstract»

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  • A structural representation for VLSI design

    Page(s): 237 - 242
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    A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<> View full abstract»

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