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25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

12-15 June 1988

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  • 25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • Automatic insertion of BIST hardware using VHDL

    Publication Year: 1988, Page(s):9 - 15
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB)

    A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion ... View full abstract»

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  • VLSI design synthesis with testability

    Publication Year: 1988, Page(s):16 - 21
    Cited by:  Papers (23)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (530 KB)

    A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design e... View full abstract»

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  • A defect-tolerant and fully testable PLA

    Publication Year: 1988, Page(s):22 - 27
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB)

    The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this t... View full abstract»

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  • Experience with the VHDL environment

    Publication Year: 1988, Page(s):28 - 33
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (445 KB)

    The authors present their work in the use of the VHDL (VHSIC Hardware Development Language) environment on three different models of DEC VAX (1, 4, and 5.8 Mips (million instruction per second)). The work included the development of a number of VHDL models and sequences of input stimuli and the gathering of performance data from their execution. Even though the set of benchmarks is not in any way ... View full abstract»

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  • The role of VHDL in the MCC CAD system

    Publication Year: 1988, Page(s):34 - 39
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distribute... View full abstract»

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  • Verification of VHDL designs using VAL

    Publication Year: 1988, Page(s):48 - 53
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB)

    VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applica... View full abstract»

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  • A module area estimator for VLSI layout

    Publication Year: 1988, Page(s):54 - 59
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<> View full abstract»

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  • Optimal aspect ratios of building blocks in VLSI

    Publication Year: 1988, Page(s):66 - 71
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (511 KB)

    A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which pr... View full abstract»

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  • A method of delay fault test generation

    Publication Year: 1988, Page(s):90 - 95
    Cited by:  Papers (55)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (574 KB)

    The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has... View full abstract»

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  • A notation for describing multiple views of VLSI circuits

    Publication Year: 1988, Page(s):102 - 107
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB)

    A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.<> View full abstract»

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  • A graphical hardware design language

    Publication Year: 1988, Page(s):108 - 114
    Cited by:  Papers (4)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Gdl is a graphical hardware design language that separates design decisions into three interrelated but distinct domains: behavioral, structural, and physical. Specific language features are provided to represent a design in each of these domains. The process model for Gdl is described. Functional behavior is separated into distinct activities called 'processes' (autonomous control centers). The c... View full abstract»

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  • A human machine interface for silicon compilation

    Publication Year: 1988, Page(s):115 - 120
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB)

    A description is given of a novel human-machine interface for use as a design environment for silicon compilation. It is important for a human machine interface to support a tool which realizes quick turn around time with little possibility of user errors. Designers should be able to work with little interference with their thinking process. To realize such a design environment, the authors have d... View full abstract»

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  • Parallel placement on reduced array architecture

    Publication Year: 1988, Page(s):121 - 127
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal ... View full abstract»

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  • Mask verification on the Connection Machine

    Publication Year: 1988, Page(s):134 - 140
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB)

    Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. A discussion is presented of the design and implementation of algorithms for several essential primitives: generation of completely intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spaci... View full abstract»

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  • On path selection in combinational logic circuits

    Publication Year: 1988, Page(s):142 - 147
    Cited by:  Papers (76)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate c... View full abstract»

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  • ATV: an abstract timing verifier

    Publication Year: 1988, Page(s):154 - 159
    Cited by:  Papers (18)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A discussion is presented of implementation and extensions of an abstract timing verifier, and in particular, several novel operations and a novel algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to ch... View full abstract»

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  • Parallel logic simulation on general purpose machines

    Publication Year: 1988, Page(s):166 - 171
    Cited by:  Papers (29)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB)

    Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processo... View full abstract»

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  • Formal specification and verification of hardware: a comparative case study

    Publication Year: 1988, Page(s):197 - 204
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB)

    A report is presented on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. The strategy consists of working with incrementally harder test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely com... View full abstract»

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  • Proving circuit correctness using formal comparison between expected and extracted behaviour

    Publication Year: 1988, Page(s):205 - 210
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB)

    A novel method is presented for verifying functionality in the design of VLSI circuits. The method fits naturally in a methodology based on a hardware description language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behavior from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to... View full abstract»

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  • Formal verification of the Sobel image processing chip

    Publication Year: 1988, Page(s):211 - 217
    Cited by:  Papers (5)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    An approach is described for hardware verification in the context of the authors' recent success in formally verifying the description of an image-processing chip. They demonstrate that their approach, which uses an implementation of an equational approach to theorem proving developed by D. Kapur and P. Narendran (1985), can be a viable alternative to simulation. In particular, they are able to ta... View full abstract»

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  • The IBM engineering verification engine

    Publication Year: 1988, Page(s):218 - 224
    Cited by:  Papers (24)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (513 KB)

    A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An o... View full abstract»

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  • Logic simulation system using simulation processor (SP)

    Publication Year: 1988, Page(s):225 - 230
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB)

    A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a ... View full abstract»

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  • Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance

    Publication Year: 1988, Page(s):231 - 236
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB)

    A very-large-scale logic simulation engine called VELVET has been developed. VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and register-transfer level structure. VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. A description is given of how to realize such high performance. An algorithm... View full abstract»

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  • A structural representation for VLSI design

    Publication Year: 1988, Page(s):237 - 242
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (505 KB)

    A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<> View full abstract»

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