Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on

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Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on

Date 6 Nov 1989

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Knowledge based test strategy planning

Synthesis by simulated annealing

IEE Colloquium on `Algorithmic and Knowledge Based CAD for VLSI' (Digest No.125)

Integrating design and verification of digital integrated circuits

Systems from architectures

Knowledge based systems used in design for testability-an an overview

Knowledge-based analogue VLSI layout synthesis

Concurrent automatic test pattern generation

Expert assistance in digital circuit design

Guaranteeing optimality in a gridless router using AI techniques

PROCEDE: a knowledge based system for designing concurrent error detecting VLSI circuits

HIT: hierarchical integrated test methodology

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