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Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on

Date 6 Nov 1989

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Displaying Results 1 - 12 of 12
  • Concurrent automatic test pattern generation

    Publication Year: 1989 , Page(s): 4/1 - 4/4
    Cited by:  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (148 KB)  

    Of the four main techniques for the automatic generation of test patterns for digital circuits the authors discuss algebraic techniques. The most widely known algebraic technique is that of Boolean Difference in which boolean functions G(X), F(X) describing the fault free and faulty circuits respectively are produced. A test function T(X) is formed from the exclusive-OR of G(X) and F(X). As an alt... View full abstract»

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  • HIT: hierarchical integrated test methodology

    Publication Year: 1989 , Page(s): 3/1 - 3/5
    Cited by:  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (280 KB)  

    In HIT a hierarchical integrated test methodology, the authors use a knowledge base to store the properties of previously characterised circuit elements called cells. Cells are divided into four categories: combinational (e.g. PLA random logic), memory (e.g. RAM, CAM), Register (e.g. latches, flip-flops, a combinational block containing a register) and Bus structures (fan-outs, bus concatenation, ... View full abstract»

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  • Guaranteeing optimality in a gridless router using AI techniques

    Publication Year: 1989 , Page(s): 6/1 - 6/4
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (256 KB)  

    Addresses the problem of automating the generation of interblock routing within the chip assembly phase of full-custom integrated circuit design. An algorithm is presented which performs routing in the gridless domain and generates the mask-layout directly from a set of user-specified design rules. The algorithm guarantees (i) to find a route if one exists and (ii) that there is no route of a less... View full abstract»

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  • Integrating design and verification of digital integrated circuits

    Publication Year: 1989 , Page(s): 8/1 - 8/6
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (240 KB)  

    Formal methods have an important role to play in the management of design information and in proving design correctness. The need is for formality to be introduced into the design process and not just to be used in post design validation. The use of relations to describe behaviour and functional style combining forms to describe circuit structure is a useful framework in which to design formally. ... View full abstract»

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  • Systems from architectures

    Publication Year: 1989 , Page(s): 10/1 - 10/6
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (212 KB)  

    Describes the benefits of synthesizing from a hardware description language (HDL). These benefits are illustrated using ELLA descriptions of simple architectures. The architectures are described at a high level of abstraction. The reference level for synthesis is raised above what was previously available. This makes it possible for system engineers to design ASICs View full abstract»

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  • Expert assistance in digital circuit design

    Publication Year: 1989 , Page(s): 7/1 - 7/3
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (120 KB)  

    An intelligent assistant for the design of microprocessor based systems from an initial set of specifications is under development. The data in the system are based on the ICs available in the market and an ASIC library of components. The aim is to enable noncomputer or nonVLSI experts to design digital systems corresponding to their requirements without having to learn the principles of digital e... View full abstract»

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  • Knowledge-based analogue VLSI layout synthesis

    Publication Year: 1989 , Page(s): 11/1 - 11/6
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (308 KB)  

    Discusses the incorporation of knowledge-based engineering for automatic layout synthesis in analogue VLSI circuits. Whilst examples are described in terms of CMOS technology, this is not restrictive and the methods described are immediately extensible to other technologies. The study involves a knowledge-based approach combined with traditional algorithmic methods to realise a design system that ... View full abstract»

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  • Knowledge based systems used in design for testability-an an overview

    Publication Year: 1989 , Page(s): 1/1 - 1/4
    Cited by:  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (216 KB)  

    In choosing a design for testability technique for a given VLSI circuit the designer must match the attributes of the technique, that is, area overhead, pin out, fault coverage, etc., against the constraints of the design specification. In the selection process, a large number of trade-offs must be considered and since there is no unified theory about the integration of design for testability stru... View full abstract»

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  • Synthesis by simulated annealing

    Publication Year: 1989 , Page(s): 9/1 - 9/4
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (176 KB)  

    Summarises work proceeding towards the development of a suite of algorithmic optimisation tools intended to operate in a directed silicon compilation environment. The tools are controlled by the stochastic computational technique known as simulated annealing. The paper contains a description of the scheduling and allocation problem, together with a description of the simulated annealing algorithm.... View full abstract»

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  • PROCEDE: a knowledge based system for designing concurrent error detecting VLSI circuits

    Publication Year: 1989 , Page(s): 5/1 - 5/8
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (372 KB)  

    The authors propose a systematic methodology for designing `reduced cost' CED VLSI circuits. The framework for the methodology is provided by the prototype electronic computer aided design tool PROCEDE (PROlog based Concurrent Error Detecting Expert). PROCEDE utilises Artificial Intelligence techniques to integrate knowledge concerning various design tasks and CED techniques applicable to various ... View full abstract»

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  • IEE Colloquium on `Algorithmic and Knowledge Based CAD for VLSI' (Digest No.125)

    Publication Year: 1989
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (12 KB)  

    The following topics were dealt with: VLSI; circuit layout CAD; design for testability; knowledge based CAD; IC testing; digital IC design; analogue IC design and circuit verification View full abstract»

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  • Knowledge based test strategy planning

    Publication Year: 1989 , Page(s): 2/1 - 2/5
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (272 KB)  

    As ICs get larger and increasingly more expensive to test, it is becoming clear that testing provision has to be made at the design stage. Brunel University are developing a Knowledge Based Test Strategy Planner, which also takes into account cost considerations. The aim is to provide designers with the advice and means for introducing an effective, realistic test plan for integrated circuits View full abstract»

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