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System Sciences, 1988. Vol.I. Architecture Track, Proceedings of the Twenty-First Annual Hawaii International Conference on

Date 5-8 Jan. 1988

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  • Proceedings of the Twenty-First Annual Hawaii International Conference on System Sciences. Vol.I. Architecture Track (Cat. No.88TH0209-7)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (68 KB)
    Freely Available from IEEE
  • High computation performance through efficient access of data structures

    Publication Year: 1988, Page(s):4 - 9
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB)

    The authors propose the use of an access coprocessor (AP) to reduce the adverse effects of the access overhead on the performance of a VLSI processor. The AP offers the possibility of achieving substantial speedup in program execution time by means of concurrency in the access and execute processes, and by the use of special operations to perform efficiently address calculations. System operation ... View full abstract»

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  • Back end architecture based on transformed inverted lists-A surrogate file structure for a very large data/knowledge base

    Publication Year: 1988, Page(s):10 - 19
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    A detailed analysis is presented of transformed inverted lists (TIL) and an inverted surrogate file structure. A parallel back-end architecture, based on TIL, is described for the management of a very large data/knowledge base. The approach relies on an inverted list-indexing scheme that is performed on the surrogate files instead of the usual database inversion applied in conventional information... View full abstract»

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  • MUTABOR-A coprocessor supporting object-oriented memory management and error recovery

    Publication Year: 1988, Page(s):20 - 29
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (926 KB)

    Part of the work done in PROFEMO (project for the design and implementation of a fault-tolerant multiprocessor system) is presented. The objective is the design of a reliable distributed system architecture and the implementation of a prototype. The approach is based on a layered, generalized transaction concept operating in an object-oriented environment. The architecture of MUTABOR, comprising a... View full abstract»

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  • HPSm2: A refined single-chip microengine

    Publication Year: 1988, Page(s):30 - 40
    Cited by:  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    The authors describe the high-performance single-chip microarchitecture of HPSm, which is being refined to provide a second chip, the HPSm2, with a 33% performance improvement. They relate how they are achieving this by making the HPS data path more regular and migrating many of the hardware functions to the compiler.<> View full abstract»

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  • A VLSI join module

    Publication Year: 1988, Page(s):41 - 49
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Some of the previously proposed join operation implementations in several database machines are briefly analyzed. An associative parallel join module and its O(n) associative parallel algorithm are proposed. A VLSI chip that has been simulated and fabricated is described, demonstrating the feasibility of the module.<> View full abstract»

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  • An exercise in high level language architecture design

    Publication Year: 1988, Page(s):50 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (629 KB)

    The semantic gap that separates programming languages from the machines on which programs are run, often resulting in poor execution efficiency, has become more of a problem with the advent of Ada, languages for artificial intelligence programming, and even Pascal-like and C-like languages, prompting research into the design of special-purpose, high-level-language-directed computer architectures. ... View full abstract»

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  • Multiple-bus multiprocessor systems

    Publication Year: 1988, Page(s):59 - 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB)

    A multiple-bus multiprocessor system (MMS) is a tightly coupled architecture that utilizes several parallel buses to interconnect multiple processors, shared memory, and shared I/O. An analysis of an MMS is presented, showing that it can provide significant processing power with a small number of buses compared to the number of processors. Results are given for the processing power in an MMS with ... View full abstract»

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  • A multi-transputer architecture for parallel logic programs

    Publication Year: 1988, Page(s):70 - 79
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB)

    An overview is presented of a scalable, 16-Transputer, mesh-connected architecture that supports a novel message-passing abstract machine model specifically designed for efficient parallel execution of logic programs. An execution model has been developed that is based on message-passing with completely distributed control, with memory references localized to each processor. A demand-driven OR-par... View full abstract»

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  • The DSI and below: The architelcture/hardware component of a computer science curriculum

    Publication Year: 1988, Page(s):81 - 84
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB)

    The authors examine the area of computer architecture and identify five courses that as a unit comprise a comprehensive treatment of undergraduate material in that area. The set of courses begins at the sophomore level with a machine-structures course and finishes at the senior level with a comparative architecture course. The authors discuss the focus of this set of courses and the rationale for ... View full abstract»

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  • Teaching computer architecture as engineering design with VLSI

    Publication Year: 1988, Page(s):85 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (566 KB)

    It is argued that to teach computer architecture is to teach engineering design of complex, multidisciplinary systems, and that to integrate that experience into an undergraduate curriculum of either computer science or electrical engineering is difficult. Students typically do not have enough breadth of experience to appreciate all the real-world concerns. It is suggested instead that VLSI be tau... View full abstract»

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  • Logic design education at Stanford University

    Publication Year: 1988, Page(s):91 - 98
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (638 KB)

    Recent developments in the logic design courses in the Computer Systems Laboratory at Stanford University are described. The courses include an introductory undergraduate lecture and laboratory course, an advanced undergraduate laboratory, and a graduate lecture and CAE (computer-aided engineering) laboratory course.<> View full abstract»

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  • Computer architecture education: An integrated classroom and laboratory experience

    Publication Year: 1988, Page(s):99 - 105
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The authors present a method by which the classroom and laboratory experience can be integrated to effectively educate the upper-division or graduate-level student. Emphasis is placed on developing problem-solving and design skills in the application of computer organizational and architectural design techniques. Specific laboratory experiences that assist this process are presented.<> View full abstract»

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  • Computer science accreditation-real needs, real concerns, real progress

    Publication Year: 1988, Page(s):106 - 110
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (477 KB)

    The Computing Sciences Accreditation Board (CSAB) approved new criteria in January 1987 in response to concerns that had been voiced about accreditation in general and its criteria in particular. The need and importance of accreditation to the computer science community is discussed, as are the concerns that have been articulated. The changes between the original and new criteria are reviewed. The... View full abstract»

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  • Observations on accreditation of computer science programs-the experience of a small liberal arts college

    Publication Year: 1988, Page(s):111 - 119
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (534 KB)

    The nature of computer science education in a small liberal-arts college environment and the applicability of accreditation and the Computer Science Accreditation Board (CSAB) criteria to computer science programs in such institutions are considered. The experience of one small liberal-arts college evaluated by CSAB, including the rationale for applying, the accreditation process, and the conseque... View full abstract»

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  • Computer science accreditation and the curriculum: a delicate partnership

    Publication Year: 1988, Page(s):120 - 123
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (299 KB)

    The computer science accreditation standards developed jointly by the Association for Computing Machinery (ACM) and the IEEE Computer Society are now in use. Computer science curriculum standards, developed separately by ACM in 1978 (and revised at the introductory level in 1984) and by the IEEE Computer Society in 1983, can play an important role in the accreditation process. The author examines ... View full abstract»

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  • SAGA and CONDENSE: a two-phase approach for the implementation of recurrence equations on multiprocessor architectures

    Publication Year: 1988, Page(s):126 - 130
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (407 KB)

    The automation of parallel implementations of algorithms, specifically those arising in scientific and engineering applications, is investigated. Since many of these computations can be formulated as coupled system of recurrence equations, they exhibit a high degree of repetitiveness and regularity. These properties are utilized to generate efficient, and in certain cases optimal, schedules and pr... View full abstract»

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  • Mapping parallel algorithms onto general-purpose parallel machines

    Publication Year: 1988, Page(s):131 - 141
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (858 KB)

    The mapping of very-high-level problem specifications to general-purpose parallel machines is addressed. The objective is to illustrate how such mappings can be successfully achieved by the implementation of a very-high-level, architecture-independent programming language. At the foundation, a macro-parallel abstract machine is devised and combined with a substitution model of functional languages... View full abstract»

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  • SVD computation on the Connection Machine

    Publication Year: 1988, Page(s):142 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB)

    The computation of the singular-value decomposition of a matrix on the Connection Machine is presented. The machine architecture is described, and it is explained why a Jacobi-type approach makes very efficient use of the available massive parallelism. Different implementation strategies are discussed for the case in which the problem size exceeds the machine size and vice versa. Encouraging timin... View full abstract»

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  • A matching approach to utilizing fine-grained parallelism

    Publication Year: 1988, Page(s):148 - 156
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (681 KB)

    An overview is presented of a system in which the compiler and architecture coordinate to match by reconfiguration. The architecture is a reconfigurable long-instruction-word machine that provides fine-grained parallelism to the compiler, which detects and schedules the parallelism in a program. The compiler uses a number of techniques to transform both the program code and architecture to obtain ... View full abstract»

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  • A dynamic-trace-driven simulator for evaluating parallelism

    Publication Year: 1988, Page(s):158 - 166
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    An efficient simulation method is presented that can model the performance of a given algorithm on an idealized multiprocessor while modeling state changes by executing equivalent code on a host processor. Characteristics of the target multiprocessor can be defined independently of the algorithm specification permitting the evaluation of an algorithm over several different machines, or conversely,... View full abstract»

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  • The effect of application characteristics on performance in a parallel architecture

    Publication Year: 1988, Page(s):167 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (505 KB)

    A shared-memory, hierarchical, clustered architecture is reported. Measurements presented (including speedups) were obtained by running six different symbolic application kernels with varying architectural parameters. The results and graphs shown highlight the manner in which application characteristics place limits on achievable parallel performance, given particular architectural features. The d... View full abstract»

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  • Reliability of the shuffle-exchange network and its variants

    Publication Year: 1988, Page(s):174 - 182
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The reliability of the shuffle-exchange multistage interconnection network (SEN) and two variations of this network aimed at improving reliability through fault tolerance is considered. The two variations are the SEN with an extra stage and the redundant SEN. Exact closed-form expressions are derived for the time-dependent reliability of the 8*8 and 16*16 SEN and SEN with an extra stage (SEN+). A ... View full abstract»

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  • TLB consistency on highly-parallel shared-memory multiprocessors

    Publication Year: 1988, Page(s):184 - 193
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (881 KB)

    Multiprocessors that store the same shared data in different caches must ensure that these caches have consistent copies. Almost all known solutions to this cache consistency problem are only suitable for architectures with a few tens of processing elements (PEs). Efficient solutions to the TLB (translation lookaside buffer) consistency problem, a special case of the cache consistency problem, can... View full abstract»

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  • Hardware support for efficient execution of Ada tasking

    Publication Year: 1988, Page(s):194 - 202
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    Several aspects of run-time support for Ada that contribute to the efficiency of the implementation are discussed. To fully support Ada, including efficient tasking, hardware support is needed. A simple method for identifying the parts of the run-time system that are good candidates for hardware support is described and used to identify three areas in which support is needed. Two kinds of smart qu... View full abstract»

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