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Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Date Feb. 29 1988-March 3 1988

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Displaying Results 1 - 25 of 106
  • Trends in scientific and engineering computing

    Publication Year: 1988
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (89 KB)

    The emerging generation of high-performance computers for scientific, engineering, and real-time applications based on parallelism and gains in VLSI is described. The machines already in use or to be available soon are briefly discussed. Training of personnel to use these computers is viewed as a barrier to progress.<> View full abstract»

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  • Design considerations for a bipolar implementation of SPARC

    Publication Year: 1988, Page(s):6 - 9
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB)

    The design of Sun Microsystems' Scalable Processor Architecture (SPARC) using bipolar emitter-coupled-logic (ECL) process is considered. The BIT1 ECL process and design considerations for an ECL implementation of SPARC are described. Bus structures, cache concerns, interface considerations, and power density are discussed.<> View full abstract»

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  • CMOS gate array implementation of the SPARC architecture

    Publication Year: 1988, Page(s):10 - 13
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (337 KB)

    A description is given of the MB86900 processor, the first implementation of Sun Microsystems' Scalable Processor Architecture (SPARC). MB86900, referred to here as the integer unit (IU), is a high-performance microprocessor designed with high-speed CMOS gate-array technology. In a typical system, the MB86900 IU works with a companion floating-point controller chip (the MB86910), two commercial fl... View full abstract»

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  • CMOS gate array implementation of SPARC

    Publication Year: 1988, Page(s):14 - 17
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB)

    A description is given of the implementation of the 32-bit RISC (reduced-instruction-set-computer)-based SPARC (Scalable Processor Architecture) microprocessor chip set MB86900 and MB86910 using a CMOS 20K gate array to meet a tight development schedule while achieving high performance with high degree of testability. MB86900 is the CPU and MB86910 is the floating-point controller. Although these ... View full abstract»

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  • CMOS customer implementation of the SPARC architecture

    Publication Year: 1988, Page(s):18 - 20
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point un... View full abstract»

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  • An implementation based on the BTRON specification

    Publication Year: 1988, Page(s):22 - 24
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB)

    BTRON is the business-oriented operating system (OS) specification of TRON (The Realtime Operating System Nucleus) and is a computer architecture for office workstations. The major objective is to offer a unified man-machine interface (MMI) and the handling of multimedia data. Data transportability has also been achieved. In order to achieve these objectives, the BTRON specification proposes a dat... View full abstract»

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  • Design considerations for 32-bit microprocessor TX3

    Publication Year: 1988, Page(s):25 - 29
    Cited by:  Papers (1)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution... View full abstract»

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  • A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100

    Publication Year: 1988, Page(s):30 - 33
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB)

    The special features of the GMicro/100 are covered, including the branching and pipelining methodologies as well as system modeling and verification. The GMicro/100 design strategies are briefly described.<> View full abstract»

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  • V60/V70 microprocessor and its systems support functions

    Publication Year: 1988, Page(s):36 - 42
    Cited by:  Papers (3)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB)

    Two advanced 32-bit microprocessors, the V60 and V70 ( mu PD70616 and mu PD70632, respectively), and their support functions for operating systems and high-reliability systems are described. Three operating system functions, namely, the virtual memory support functions, context-switch functions, and asynchronous trap functions are examined. A basic mechanism for high-reliability-system implementat... View full abstract»

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  • Architecture of the WE32200 chip set

    Publication Year: 1988, Page(s):43 - 47
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (379 KB)

    Four members of the WE32200 chip set are described. They are the WE32200 central processing unit (CPU), the WE32201 memory management unit (MMU), the WE32204 direct memory access controller (DMAC), and the WE32206 math acceleration unit (MAU). These chips constitute the VLSI core of a general-purpose computing environment supporting virtual memory and IEEE standard floating point arithmetic. The i... View full abstract»

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  • Regulus: A high performance VLSI architecture

    Publication Year: 1988, Page(s):48 - 50
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (261 KB)

    A description is given of the Regulus processor, a high-performance microprocessor designed to take full advantage of custom VLSI. The general-purpose 32-bit Regulus architecture is designed to minimize control area and maximize the amount of on-chip memory. The instruction set is very simple, with memory addressed only through load and store instructions. The first design is implemented with a 1.... View full abstract»

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  • Intelligent control of robot manipulators in hazardous environments

    Publication Year: 1988, Page(s):54 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The characteristics of hazardous environments and the impact these have on robot manipulator system control are reviewed. In particular, computer-based reasoning must be integrated into the control of robot manipulators to allow successful application to such environments. Computing architectures and the concomitant software structures necessary to support both the high-level reasoning and low-lev... View full abstract»

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  • Artificial intelligence and robotics

    Publication Year: 1988, Page(s):59 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB)

    It is argued that the artificial intelligence (AI) and robotics communities, although addressing similar problems, typically focus on very different aspects of those problems. The two fields interact profitably in the area of building intelligent agents; this interaction has resulted in important developments in the areas of vision and planned action. It is suggested that to allow further progress... View full abstract»

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  • Prolog at Berkeley

    Publication Year: 1988, Page(s):64 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB)

    An overview is given of the Aquarius project at Berkeley, which is centered on the high-performance execution of logic programs in general and Prolog in particular. Its goal is to determine how a very large improvement in performance can be achieved in a machine specialized to solve difficult problems characterized by symbolic and numerical calculations, both within a search space. The particular ... View full abstract»

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  • Prolog at the University of Illinois

    Publication Year: 1988, Page(s):68 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB)

    A brief description is given of four logic programming research projects currently underway. Three projects deal with the design of Prolog interpreters and compilers; the other deals with the design of languages that combine the functional programming and the logic programming paradigms and with the transformation of programs written in these languages.<> View full abstract»

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  • Logic programming research in Oregon

    Publication Year: 1988, Page(s):74 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    An overview is given of various research projects at the University of Oregon and elsewhere in the state of Oregon. The projects at the University of Oregon are studying closed environments. OM (the OPAL Machine), and object-oriented program with logic work at other research centers is mentioned briefly.<> View full abstract»

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  • Parallel programs in the Cray and on the Alliant: a comparative evaluation

    Publication Year: 1988, Page(s):82 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (127 KB)

    The microtasking capabilities of two computers are examined. Microtasking is a loop-based form of multitasking on MIMD (multiple-instruction, multiple-data-stream) computers in which much of the synchronization and control of parallel tasks in a user's program is managed by vendor software. Differences in the microtasking features of Cray X-MP/4 and Alliant FX/8 are described, the processes of app... View full abstract»

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  • Challenges in matching parallel architectures and matrix algorithms

    Publication Year: 1988, Page(s):84 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB)

    Direct solution methods based on Gauss elimination and its variants are considered. These are of particular interest because they readily expose memory limitations and communication bottlenecks of parallel architectures, are integral components of other, more highly parallel matrix algorithms, and can solve poorly conditioned problems on which other methods fail. The parallel implementation and pe... View full abstract»

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  • The good, the bad and the ugly: comparing high speed computer systems

    Publication Year: 1988, Page(s):90 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (509 KB)

    Several different classes of high-speed computer systems for scientific computing are investigated. These include mainframes, mainframes with vector facilities, minisupercomputers, vector supercomputers, and vector-multiprocessor minisuper and supercomputers. A finite-difference elastic wave code is run on several high-speed systems. The numerical scheme is based on a dimensional splitting that le... View full abstract»

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  • Programming and performance on a cube-connected architecture

    Publication Year: 1988, Page(s):97 - 100
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB)

    The strengths and weaknesses of the first generation of commercial hypercube multiprocessors and their effects on software development and implementation are examined. Program loading, language, debugging, communications, algorithms, and load balance are considered. These issues are addressed with respect to hypercubes of a thousand or more processing elements.<> View full abstract»

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  • Digest of Papers: COMPCON Spring 88. Thirty-Third IEEE Computer Society International Conference (Cat. No.88CH2539-5)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (41 KB)
    Freely Available from IEEE
  • Experiences with the BBN Butterfly

    Publication Year: 1988, Page(s):101 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB)

    Collective experience using the BBN Butterfly Parallel Processor, a shared-memory multiprocessor built around a scalable high-bandwidth switching network is described. An overview of the Butterfly hardware, run-time library is given. While the Butterfly provides a high performance testbed for parallel processing research, it has been found that its lack of a file system and a strong development en... View full abstract»

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  • Cydra 5 directed dataflow architecture

    Publication Year: 1988, Page(s):106 - 113
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB)

    A description is given of a balanced and functionality complete minisupercomputer called the Cydra 5 Departmental Supercomputer. The Cydra 5 makes extensive use of industry standards, such as AT&T Unix System V.3, ANSI Fortran 77, and the IEEE 754 floating-point standard, to take advantage of customers' investments in applications software. The open architecture of the Cydra 5, including the use o... View full abstract»

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  • Symmetry: a second generation 'practical parallel'

    Publication Year: 1988, Page(s):114 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (133 KB)

    In the last three years there has been over a fourfold improvement in the raw processor performance of VLSI integrated processors with a corresponding increase in the memory bandwidth demand. The author explores the issues of managing this increased bandwidth while retaining compatibility with a first-generation shared-memory, bus-based, symmetric, transparent multiprocessor.<> View full abstract»

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  • The Supertrek S-1 mini-supercomputer

    Publication Year: 1988, Page(s):116 - 118
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (173 KB)

    A description is given of the Supertrek S-1, a Cray X-MP/416-compatible minisupercomputer that offers 40-MFLOPS (floating-point operations per second) peak performance. It is implemented in advanced high-speed TTL/CMOS technologies. The system features compactness, low power consumption, and high reliability/maintainability. The S-1 design was optimized for the Cray X-MP architecture, using centra... View full abstract»

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