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Analogue IC Design: Obstacles and Opportunities, IEE Colloquium on

Date 18 Jun 1990

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Displaying Results 1 - 10 of 10
  • Device modelling and design techniques for analogue SOS circuits

    Publication Year: 1990 , Page(s): 8/1 - 8/5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    Silicon-on-sapphire (SOS) has become a popular technology for the implementation of digital integrated circuits for use in radiation environments. The reason for this is the complete isolation of devices by the insulating substrate, which ensures latch-up immunity under transient irradiation. An additional benefit is the very low parasitic capacitances which bestow good circuit speed. For analogue applications, the use of dielectrically isolated structures, which includes emerging silicon-on-insulator (SOI) technologies, opens up the possibility of incorporating MOS and bipolar devices on the same substrate, and offers higher design flexibility. Also, high quality polysilicon-oxide-diffusion capacitors can be made without the pn-junction parasitics found in equivalent bulk CMOS structures. The design of analogue circuits in SOS presents a number of problems, however, which have to be overcome if good analogue performance is to be achieved both in the absence of and during irradiation View full abstract»

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  • Specification capture and yield enhancement in an interactive environment

    Publication Year: 1990 , Page(s): 2/1 - 2/5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    Describes a new tool for the analogue circuit designer, a tool concerned particularly with component tolerances and the unwanted effect these have on the performance of a mass-produced circuit. It assists in the redesign of a circuit to increase the manufacturing yield and reduce component costs. Like some conventional tools, this one simulates the effect of component variations on circuit performance and, by checking against performance specifications, estimates the manufacturing yield. Unlike others, however, it not only provides the designer with diagnostic information regarding especially sensitive parameters and specifications, but will also automatically adjust the nominal values of components in order to maximise the yield. Any parameter, such as the width of a device or the value of a resistor, may be designated as adjustable by the designer View full abstract»

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  • IEE Colloquium on `Analogue IC Design: Obstacles and Opportunities' (Digest No.107)

    Publication Year: 1990
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    The following topics were dealt with: CAD; layout; testing; signal processing; applications View full abstract»

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  • Analogue IC design within EUROCHIP

    Publication Year: 1990 , Page(s): 1/1 - 1/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    The UK's own very successful ECAD Initiative (Electronics CAD) is now of several years standing and has made general CAD tools and IC design available to some 100 participating HE and FE institutions. This UK scheme, funded on a start-up basis by the (then) UGC (for the universities) and NAB (for the polytechnics and colleges), and with chip fabrication currently subsidised by the DTI, may in some senses be viewed as having provided a model for the more recent European venture, EUROCHIP, which is described in this paper View full abstract»

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  • Layout tool for high speed electronic and optical circuits

    Publication Year: 1990 , Page(s): 3/1 - 3/5
    Cited by:  Patents (13)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    At present, gallium arsenide, silicon-bipolar, integrated and holographic optics are starting to emerge as potential technologies for designing VLSI circuits. Their use will certainly require a review on the concepts of layout tools, and new algorithms may be included in such systems. This is particularly true for the design of holographic optical interconnection, which is a promising way of bringing optics into electronic circuits in order to alleviate the present VLSI communication problems. An algorithm for holographic optical interconnection is discussed. For this application it is important that the data structure can represent curved shapes. A corner-stitching based data structure that can represent rectangles, trapezoids and curved shapes is discussed View full abstract»

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  • A multichannel signal processor IC [for sonar]

    Publication Year: 1990 , Page(s): 6/1 - 611
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    One particular mode of active sonar signal processing is that of Doppler Processing, where a narrowband transmission and a spectral analysis receiver use the Doppler shift in frequency to discriminate moving wanted targets from stationary unwanted ones, such as returns from the sea surface or sea bed. A bank of filters matched to the transmission pulse duration provides the essential element of a Doppler processor but typical sonar parameters result in the requirement for very narrow bandwidths and a large number of filters to cover the range of anticipated Doppler shifts in frequency. Increasing the filters' bandwidths before detection but maintaining an appropriately narrow post-detection bandwidth eases the design problems without appreciably sacrificing overall detection performance. Such an approach has resulted in the integrated circuit design to be described View full abstract»

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  • Analogue IC design using switched-currents

    Publication Year: 1990 , Page(s): 7/1 - 7/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    Most IC signal processors employ digital techniques with an analogue interface to the outside world. Frequently, the analogue interface employs switched-capacitor circuits performing A-D or D-A conversion, sample and hold, filtering etc. Unfortunately, switched-capacitors have never been compatible with VLSI processing as they invariably employ special processing options to make linear capacitors. As IC processing shrinks into the sub-micron region necessitating lower supply voltage working, switched-capacitors will suffer performance degradation. To overcome these problems `switched-currents' were introduced about one year ago. Since then, the technique has undergone a number of developments. These include re-definition of the integrator structure to improve component sensitivity, noise, speed and linearity. Differentiator structures have also been introduced. Either integrators or differentiators may be used as building blocks for implementing signal processors using design-automation techniques. The circuits have inherent high bandwidth since they do not employ operational amplifiers. The paper will describe these recent developments which make the switched-current technique a real contender to succeed switched-capacitors in future VLSI systems View full abstract»

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  • Towards a new generation of analogue IC design architectures

    Publication Year: 1990 , Page(s): 9/1 - 916
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    More mature device technologies such as true complementary silicon bipolar junction (BJT), mixed silicon bipolar and complimentary metal oxide semiconductor devices (BiCMOS) and Gallium Arsenide (GaAs) are becoming available and bring with them the requirement for novel analogue design, methods, techniques and CAD tools necessary for the successful development and exploitation of these technologies for the future market place. Coupled with these technological improvements are the ever shrinking feature size of devices on ICs and the consequential reduction of power supply voltages which has fuelled the creation of `alternative' analogue design methods. This paper is a review of some of the authors' work on the design and application of current-mode analogue signal processing techniques and the development of a new generation of high performance analogue circuit and system architectures, with emphasis on high speed View full abstract»

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  • Can digital tests be used on analogue integrated circuits?

    Publication Year: 1990 , Page(s): 5/1 - 5/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    The increasing availability and reduced cost of mixed analogue/digital ASICs means that it is possible to design and fabricate such circuits in small quantities in a short space of time. However the generation of tests to determine whether the chips have been correctly manufactured is not so straightforward. Purely digital circuits are usually tested using the stuck-at fault model to generate test patterns which highlight faulty devices, but no such process exists for mixed-signal circuits where the interface between digital for and analogue sections may be inaccessible to test probes. Design-for-test techniques may be used to overcome this problem by including test circuitry on the chip that allows the digital and analogue sections to be tested independently; but this involves the use of additional pins, silicon and design time, all of which are unacceptable in a low-volume, short-timescale project. Work at Lancaster is looking at ways of avoiding these complications by using pseudo-digital tests to check the functionality of a complete chip (which may be composed entirely of analogue cells) using readily available digital test equipment. This paper discusses the approach used and the fault cover that can be expected View full abstract»

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  • The automated improvement of analogue integrated circuits

    Publication Year: 1990 , Page(s): 4/1 - 4/5
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Concerns techniques whereby a computer automatically suggests new values for certain designable parameters with a view to improving circuit performance. There are many reasons why one needs such techniques for the automated improvement of integrated circuits. In the most familiar case the designer may have done the best he or she can, and produced a circuit which meets specifications, but wishes to discover whether any improvement is possible via the adjustment of parameter values. Or a circuit may have been passed to a layout module and the extracted parasitics added to the circuit model to produce what is, in effect, a new circuit which must be readjusted to satisfy the specifications. Alternately, within one of the emerging analogue synthesis systems, some simple design rules may have been used to automatically generate a `first cut' circuit design which then needs to be adjusted to bring it closer to the desired performance. Further adjustment may also be needed, in a procedure called tolerance design, to compensate for the reduction in manufacturing yield which might occur due to the inevitable tolerances on component values View full abstract»

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