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VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE

Date 12-13 June 1990

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  • 1990 Proceedings. Seventh International IEEE VLSI Multilevel Interconnection Conference (Cat. No.90TH0325-1)

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    Freely Available from IEEE
  • Evaluation of laser planarized second aluminum for semiconductor devices

    Page(s): 90 - 96
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    Laser planarization was applied to the second layer of metallization of a static memory part. Electrical evaluation by means of chain resistance, contact chain resistance, metal continuity/shorts, and leakage showed no deleterious effect for the laser planarized parts when compared to the control split, while SEM cross-sections showed fully planarized vias and large grain size for the metal. An electromigration study conducted to evaluate the effect of laser planarization on reliability indicated that an improvement in electromigration resistance, as compared to the control split, is attained when the metal is submitted to laser planarization View full abstract»

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  • Advantages of dual frequency PECVD for deposition of ILD and passivation films

    Page(s): 194 - 201
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    The advantages of dual-frequency plasma-enhanced chemical vapor deposition (PECVD) for the deposition of silicon nitride, oxynitrides, and TEOS oxide films are discussed, and a mechanism explaining the effects on step coverage, film stress, chemical composition, and film density and stability is proposed. It is shown that the use of dual frequency for PECVD of dielectrics provides increased flexibility and process control. The main role of the high-frequency RF is to generate the reactive species and provide sufficient electron and ion densities. The low frequency is added to control the ion bombardment to which the substrates are subjected during deposition. Increasing the low-frequency power increases the plasma potential and the amount of ions following the low-frequency RF field (<1 MHz). The resulting low-energy ion implantation occurring during deposition causes a change in the intrinsic film stress from tensile to compressive, increases film density, and improves the chemical reactions. In addition, the low-energy bombardment enhances the surface mobility of adsorbed TEOS and Si(NH2)x, thus improving the step coverage of TEOS SiO2, standard silicon nitride, UV transparent nitride, and oxynitrides. However, if the ion energy is too high, the step coverage deteriorates due to premature decomposition of the reactive species View full abstract»

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  • Sticking coefficient as a single parameter to characterize step coverage of SiO2 processes

    Page(s): 404 - 406
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    The authors use a single parameter, the sticking coefficient (or reaction probability), to model the step coverage of low pressure chemical vapor deposited (LPCVD) SiO2 films. Earlier studies show that a low sticking coefficient, instead of surface diffusion, is the key step coverage improving mechanism. A simulation program based on a hypothesized reaction mechanism has been written to simulate deposition profiles. The program is capable of simulating redeposition and surface diffusion. Simulated profiles, using a single sticking coefficient (SC), agree well with experimental oxide films deposited on a variety of different geometries. The coefficient depends strongly on the silicon source used, and its magnitude decreases with increasing temperature View full abstract»

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  • Improved CVD aluminum deposition using in-situ sputtered nucleation layers

    Page(s): 303 - 309
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    Superior-quality chemical vapor deposited (CVD) Al films have been achieved using tri-isobutylaluminum (TIBA) on in-situ sputtered nucleation layers. The nucleation layer enhances the growth of CVD Al, resulting in smooth, high-quality films suitable for VLSI application. The use of in-situ sputtered seed layers allows the deposition of CVD Al on SiO2 without having to expose the wafers to TiCl4 , which may leave Cl residue and cause corrosion. In addition, the CVD films deposited on a TiN seed layer demonstrate smooth morphology and high conductivity and show no presence of the pinholes or interfacial voids which rendered earlier CVD Al films unusable for VLSI. The TIBA process is done at low temperature of 250°C, and TiN is an accepted barrier metal. The combined TiN/CVD Al process promises a low-cost, high-quality manufacturable process for VLSI metallization View full abstract»

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  • Interconnect noise analysis for megabit DRAMs

    Page(s): 205 - 211
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    Analytical noise modeling of the bit line coupling analysis for various DRAM architectures has been developed. Intrabit and interbit line coupling for true folded, interdigitated, and twisted architectures are analyzed. Analytical equations for the noise-to-signal ratio are derived based on the charge conservation and the current continuity equations. The time-dependent differential equations for twisted architectures are presented. The analytical expressions provide insight into the charge redistribution when the word lines turn on. The topology for array noise extraction in SPICE circuit simulation is presented. SPICE simulations are found to be in good agreement with the analytical results View full abstract»

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  • Integration of an in situ RIE preclean with a CVD tungsten silicide deposition process

    Page(s): 462 - 467
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    The in situ process capability of native oxide removal affords an advantage over the conventional method of aqueous hydrofluoric acid cleaning prior to a film deposition step. A technique is described in which an in situ predeposition clean with C2F6 gas, using reactive ion etching (RIE) prior to tungsten silicide deposition, is employed. This technique allows post-silicide-deposition high-temperature heat treatment and wet oxidation without loss of film adhesion or other obvious degradative effects. Also reported is the use of secondary ion mass spectrometry (SIMS) to show that this procedure has been effective in the removal of the oxide layer prior to silicide deposition. This study includes definition of the RIE etch parameters which provide acceptable etch selectivity of the oxide to silicon, and avoidance of excessive fluoropolymer formation on the silicon surface View full abstract»

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  • Enhanced selective tungsten encapsulation of TiW capped aluminum interconnect

    Page(s): 289 - 295
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    With the use of the encapsulation barrier metal technique, the metal 1 thickness can be reduced due to the structure's high resistance to electromigration. With the thinning of metal 1, the thickness of the interlevel dielectric can be reduced within capacitance constraints with minimal concern for hillocking during the oxide deposition. With the thinning of metal 1, the interlevel deposition topography becomes more planar. This process enhancement permits the use of selective tungsten plugging of vias in that the tungsten fluorine barrier acts as a seed layer at the base of the via. This technique can be used in an n-level metalization process by repeating the metal 1 encapsulation process on subsequent metal interconnect levels View full abstract»

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  • Manufacturable triple level metal technology for submicron CMOS

    Page(s): 407 - 409
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    The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and evaluate the processes. Electrical measurements and physical analysis are presented for these components View full abstract»

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  • A thermally stable salicide process using N2 implantation into TiSi2

    Page(s): 310 - 316
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    TiSi2 is an appropriate candidate for the self-aligned silicide (salicide) process. However, it degrades morphologically and the film sheet resistance increases during high-temperature annealing. A thermally stable salicide process using N2 implantation into TiSi2 has been developed in order to retard this phenomenon. The morphology of the TiSi2 film and the film sheet resistance were evaluated as a function of implanted N2 dose after high-temperature annealing. The sample which received the highest dose exhibited the best film morphology, while there is an optimum dose for maintaining the film sheet resistance at its maximum value. The dependence of sheet resistance on implanted N2 dose is discussed in terms of agglomeration, film composition, and implantation damage. A successful application to a submicron MOS transistor is presented View full abstract»

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  • A contact electromigration study of Al-Si-Cu alloys

    Page(s): 351 - 353
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    With the advent of VLSI device density, new materials and technologies are being developed to ensure that interconnects and interlevel contacts are reliable. In addition to the use of Si-doped Al, barrier metallization has been introduced to prevent electromigration-induced junction spiking. To permit increased current densities, Cu has also been added to the Al alloy. It could be argued that with the use of a barrier metal, silicon in the Al alloy can be removed altogether. The experiments reported were designed to ascertain the validity of this argument. Three different aluminum alloys were investigated: Al-1%Si, Al-2%Cu, and Al-1%Si-0.5%Cu. A sample of 90 devices were tested in each case. The failure criteria chosen were a 50% increase in resistance of 50 μA of leakage to substrate. The major failure mechanism for all three alloys was found to be resistance increase at the contact where electrons flow from the silicon into the aluminum, due to electromigration of aluminum away from the contact area. The significantly higher values of median time to failure for the two alloys containing copper reflect the higher resistance to electromigration of these alloys View full abstract»

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  • The effect of CVD W/TiW metallization on very shallow CoSi2 junctions

    Page(s): 319 - 321
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    The effect of Al/CVD W deposition on shallow junctions below CoSi 2 using 450-1800-Å sputtered TiW as a barrier/glue layer is investigated. The thermal stability of the Al/CVD W/TiW/CoSi 2 structure is studied by comparing the reverse bias current of the initial diodes with that after annealing the structure. The results for the deeper n+(P)/p diodes ~1000 Å below ~700-Å CoSi2 are different from those for the p+ (BF2)/n diodes ~500 Å below CoSi2. When the TiW is >450 Å thick, Al/CVD W does not degrade the n +/p diodes. The reverse bias current is <10 nA/cm2 when the Al/CVD W/900-Å TiW is annealed at up to 450°C for 60 min. The n+/p diode sport population increases when CVD W is deposited on 450-Å TiW. The diodes are severely degraded after 3000-Å Al is sputtered at 300°C. The temperature of CVD W deposition affected the degradation of the p+/n diodes. Higher-temperature depositions at ~500°C degraded these diodes less than depositions at ~300°C. However, annealing the Al/CVD W/900-Å TiW/CoSi2 p+/n structures at 400°C for 30 min degrades the diodes independently of the CVD W temperature where 300<T<500°C View full abstract»

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  • Electron cyclotron resonance (ECR) deposited SiO2 films for interlayer dielectric application

    Page(s): 381 - 383
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    Summary form only given. A study of ECR-CVD oxide for interlayer dielectric deposition is reported. Films have been characterized by various techniques such as stress, Fourier transform infrared (FTIR), etch rate, refractive index, breakdown field, and dielectric constant. The film properties and some process integration issues are discussed. C-V and I-V characteristics of an ECR-CVD deposited oxide indicate an 11-MV/cm breakdown field and 4.0 dielectric constant. Stress vs. temperature curves are shown for films deposited with substrate RF bias and without bias. A planar oxide surface on both a high-aspect-ratio gap and a contact topography is shown. As the RF bias increases, the deposition rate decreases, the Si-O peak width narrows, the film stress reduces, and the wet etch rate reduces. The threshold voltage shift caused by UV radiation when microwave power increases is shown View full abstract»

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  • Metal-voiding phenomenon in aluminum and its alloys

    Page(s): 127 - 132
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    It is shown that metal void generation is not a single-dimensional problem. The extent of voiding was found to be related to metal deposition conditions, the presence and extent of solutes (Si, Cu), the etch process, the postetch cleaning process, the passivation material and postpassivation temperature cycling. A simple, rapid (5-min), nondestructive technique, thermal wave imaging (TW1) is presented. It allows for the accurate determination of the extent of cracking in metal lines that are underneath passivation films. This technique is compared with backscatter electron (BSE) imaging, which is also capable of looking at cracks through passivation films. Thermal wave data on the impact of accelerated aging of devices (at 400°C) on metal voiding are presented View full abstract»

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  • Effects of contact hole filling and multilevel metallization on gate oxide integrity and transistor performance

    Page(s): 113 - 119
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    Effects of tungsten and polysilicon contact hole fillings as well as multilevel metallization on gate oxide integrity and transistor performance are evaluated. The data indicate that back-end processing may deteriorate gate oxide quality and hence degrade transistor performance. Monitoring gate oxide damage as a function of metallization process steps revealed severe oxide damage which is mainly generated by reactive ion etching and metal sputtering. However, subsequent processing at elevated temperatures (e.g. oxide or polysilicon deposition) efficiently reduced gate oxide damage prior to the final forming gas anneal. In the case of polysilicon contact hole filling this results in extremely low interface trap densities on fully processed wafers and excellent device characteristics. In contrast, severe degradation of transistor performance was found in the case of tungsten contact hole filling View full abstract»

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  • Electromigration resistance of TiN-layered Ti-doped Al interconnects

    Page(s): 360 - 362
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    The electromigration performance of 2-μm-wide, 17-mm-long single-layer and TiN-layered Al interconnects was studied. Al-1%Si-0.15%Ti and Al-0.15%Ti-based films were sputter deposited at 200-300°C and 475°C substrate temperatures, respectively. The interconnect lifetime improved dramatically when Al-0.15% Ti alloy was used instead of Al-1%Si-0.15%Ti. A TiN underlayer reduced the Al alloy EM resistance, except when the TiN was exposed to air prior to Al deposition View full abstract»

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  • In-situ stress changes of WSix film during polycide process sequence

    Page(s): 261 - 267
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    In-situ stress changes of capped and uncapped sputtered tungsten silicide films were studied. In addition, film resistivity, grain size and film morphology as a function of temperature were examined. Rutherford backscattering (RBS), X-ray diffraction (XRD), and transmission electron microscopy (TEM) were used to determine film composition, morphology, and grain size. The stress characteristics were used to calculate activation energies for the phase change induced by high-temperature processing of these films. The activation energies for the transformation from the amorphous to the metastable hexagonal phase and from that to the stable tetragonal phase were determined to be 2.04 eV and 3.66 eV, respectively. The coefficient of thermal expansion was found to be identical for both the phases of tungsten silicide and was calculated to be 15.45E-6/°C. The information reported in this study can be used to calculate the stress in the tungsten silicide film at every step of the polycide process sequence and to optimize the process conditions to minimize the stress in the film. The importance of the temperature of deposition of the cap oxide film is shown View full abstract»

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  • Experimental study of metal-metal contact properties using spin on glass

    Page(s): 447 - 449
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    Degassing data of cured spin-on glass (SOG) layers and wafer temperature measurements during the sputter etch process are given. A solution for the metal-metal contact problem using an in situ preheat step prior to a (soft) sputter etch process and subsequent metal deposition is presented. An improvement in IN-INS contact string resistance yield from approximately 40% to 99.5% could be achieved in this process View full abstract»

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  • Filling of contacts and interconnects with Cu by XeCl laser reflow

    Page(s): 431 - 434
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    The process window for XeCl laser (λ=308 nm) induced reflow of sputter-deposited Cu film to planarize and fill 1-μm-diameter contacts and 1-μm-wide interconnect trenches in a 1- or 2-μm-thick BPSG layer was investigated at room temperature, 365°C, and 440°C. Complete filling of 1-μm contacts and trenches with an aspect ratio of 1 is possible with an appreciable process window, but filling of these same contacts and trenches with an aspect ratio of 2 is only possible at a substrate temperature of 440°C. The properties of the Cu films, such as sheet resistance, reflectance, grain size, and stress, were also characterized as a function of laser fluence at room temperature, 365°C, and 440°C View full abstract»

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  • Multilevel interconnection and electrode separation technology using anodic oxidation and application to unidirectional surface acoustic wave transducers

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    Summary form only given. A description is given of a new multilevel interconnection using a technology in which surfaces of electrodes connected to the anodic oxidation power source are oxidized and changed to the dielectric layers. The surfaces of unconnected electrodes do not change and can be fabricated by using a simple photomask and rough mask alignment. Also described is a new electrode separation fabrication technology using a liftoff anodic oxidation method. Electrode separations are obtained using dielectric thin films fabricated by anodic oxidation of the edge of an Al film covered by the photoresist. The fabrication technology has the following merits: (1) controllable narrow gaps between electrodes with good insulation; (2) a wide electrode with small resistance; and (3) a wide photomask View full abstract»

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  • An investigation of device instabilities arising from the encapsulation material and composition

    Page(s): 354 - 356
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    Two factorial experiments were designed to identify process variables and material compositions for improving hot-carrier-induced MOSFET device instability. The first experiment was designed to identify what factors related to the passivation process are most important. The second experiment concentrated on the composition and thickness of the double-layer nitride-oxide passivation. The results indicate that improvement is achieved by adding an oxide layer under the plasma silicon nitride and performing a sinter prior to the nitride deposition rather than afterwards. The most significant factors were the nitride composition, the thickness of the oxide layer, and the sinter atmosphere View full abstract»

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  • A new caged structure spin-on-silica for multilevel interconnect application

    Page(s): 180 - 186
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    A unique, carbon-free silica material, based on a new concept of converting caged (HSiO3/2)n structures by eliminating the hydrogens and cross-linking the caged structures with oxygen, was characterized for ILD (interlayer dielectric) applications. The films show excellent uniformity as well as good planarity. At temperatures below 600°C, no volume shrinkage is observed. However, above this temperature, volume losses of as much as 30% can be observed. FTIR (Fourier transform infrared) spectroscopy data and film stress measurements (used to determining film stability) show that a stable crack-free oxide (SiO2) can be obtained with a high-temperature oven bake or with an optimized process combining low-temperature oven baking and exposure to oxygen plasma. These early results show that this spin-on-silica precursor is suitable for nonetchback processes such as those that involve oxide deposition between polysilicon and the first level of metal. With processing improvements at lower temperatures, the precursor also shows promise for intermetal oxide applications View full abstract»

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  • Sequential sputter deposition of titanium nitride and aluminum

    Page(s): 338 - 341
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    A sequential deposition process (without air exposure or postdeposition anneal) in a multichamber UHV magnetron sputter deposition system is described. The TiN film has low resistivity (40 μΩ-cm), low stress (0.23×109 dyne/cm2 ), and excellent diffusion barrier properties; it is stable after a 600°C, 30-min anneal. For nonoptimum films, a RF bias is shown to enhance the TiN barrier property. Oxygen addition during deposition increases film resistivity. Air exposure forms a titanium oxide layer in the Al-TiN interface, reducing the diffusion of titanium from TiN into aluminum View full abstract»

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  • Time resolved reflectivity measurements of Al alloys during excimer laser planarization

    Page(s): 83 - 89
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    Time-resolved reflectivity measurements have been made in situ during XeCl (λ=308 nm) excimer laser planarization of Al, AlSi(1%), and AlSi(1%)Cu(0.5%) at 25, 250, and 400°C. The reflectivity change observed when using a HeNe (λ=632.8 nm) probe beam is assumed to indicate layer melting. Metal melt times have been determined as a function of laser energy fluence, substrate temperature, and oxide thickness. The results show that metal melt times increase with laser energy fluence and substrate temperature, the pure Al melts for shorter times and needs higher laser energy fluences than the corresponding alloys, and little difference is seen in the melting characteristics of the alloys. The best conditions for insuring complete planarization (long melt times) would thus be for conditions in which the wafer is heated View full abstract»

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  • Effect of barrier metal under first aluminum layer on reliability of interconnect vias and contact

    Page(s): 368 - 370
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    It is shown that the lifetime due to electromigration is affected by the barrier metal under the first aluminum layer. The reliability of interconnect vias and contacts is greatly improved by using Ti/TiN barrier metal. The effect of barrier metals can be explained by the presence of Si nodules and hillocks at vias. In aluminum with MoSi, many Si nodules induced by MoSi were observed. These Si nodules degrade the reliability of interconnect vias. On the other hand, in aluminum with a Ti/TiN barrier, Si nodules and hillocks were extremely few View full abstract»

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