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Application and Development of the Boundary-Scan Standard, IEE Colloquium on

Date 19 Dec 1990

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  • The IED boundary scan project

    Publication Year: 1990, Page(s):7/1 - 7/6
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (184 KB)

    In December 1989, a proposal was put forward jointly by Plessey Roke Manor Research, British Aerospace, and Southampton University under the Advanced Technology Programme of the IED. This proposal was approved, and was intended to start in July 1990; unforeseen circumstances intervened, however, so that essentially the same project will now be run with Plessey, ICL, and Southampton, and is expecte... View full abstract»

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  • Experience of designing JTAG ASICS within System X

    Publication Year: 1990, Page(s):5/1 - 5/3
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (128 KB)

    Describes some of the experience gained when using the Boundary Scan technique, as proposed by the Joint Test Action Group (JTAG), for Application Specific Integrated Circuit (ASIC) design at GEC Plessey Telecommunication (GPT) in Poole; and offers some thoughts on the advantages and disadvantages of the JTAG method View full abstract»

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  • Applications and onward development of ANSI/IEEE Std 1149.1

    Publication Year: 1990, Page(s):1/1 - 1/7
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (192 KB)

    Many companies, encouraged by the recent introduction of ANSI/IEEE Standard 1149.1 are starting to use boundary-scan techniques for testing loaded PWBs. Applications and future developments of this standard are discussed View full abstract»

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  • IEE Colloquium on `Application and Development of the Boundary-Scan Standard' (Digest No.183)

    Publication Year: 1990
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (20 KB)

    The following topics were dealt with: ANSI/IEEE standard; JTAG; memory controllers; system level test; ASICs; fault algorithms; IED View full abstract»

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  • Boundary scan design for a memory controller

    Publication Year: 1990, Page(s):3/1 - 3/2
    Cited by:  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (168 KB)

    A boundary-scan design that fully conforms to the IEEE 1149.1 standard has been incorporated in MEMC2, a complete memory and system controller for ARM-based systems. MEMC2 provides a two level memory management system: Level 1 Page Tables are stored on-chip for improved access speed while the larger Level 2 Tables are stored in main memory. An on-chip 64-entry Translation Lookaside Buffer of Level... View full abstract»

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  • Bridging fault algorithms for a boundary scan board

    Publication Year: 1990, Page(s):6/1 - 6/8
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    Although the introduction of boundary scan reduces the need for in-circuit testing via a bed-of-nails fixture, the time taken to load a test vector serially places a new premium on minimising the number of test vectors. In addition, net testing via a boundary scan has to rely on detecting standard voltage level changes rather than the resistance-related tests possible with in-circuit testing. This... View full abstract»

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  • An initial design study of the use of boundary scan to simplify system test [guided weapons]

    Publication Year: 1990, Page(s):4/1 - 4/5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (252 KB)

    The Defence Division (DD) of Thorn EMI is currently developing a servo-system for a gimballed transceiver as part of a seeker system to be installed in a missile. In order to enhance the test access at the component, board and assembly levels, the use of boundary scan circuits in an ASIC implementation has been addressed. The purpose of this paper is not to review the detailed benefits which have ... View full abstract»

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  • ICL's first development using IEEE 1149.1 (JTAG)

    Publication Year: 1990, Page(s):2/1 - 2/3
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (116 KB)

    Outlines the first ICL gate array product selected to explore the advantages and opportunities of using the emerging (JTAG) boundary scan architecture View full abstract»

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