IEEE Proceedings of the Custom Integrated Circuits Conference

13-16 May 1990

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Displaying Results 1 - 25 of 168
  • A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

    Publication Year: 1990, Page(s):4.4/1 - 4.4/4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (243 KB)

    The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface... View full abstract»

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  • A hybridised, multi-channel, charged-particle detecting and counting array

    Publication Year: 1990, Page(s):15.7/1 - 15.7/4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (318 KB)

    A hybrid circuit is reported which is a novel position-sensitive charged-particle detector. Multiple-anode integrated detectors (MAIDs) have been developed which consist of an array of electron sensing anodes and a corresponding array of amplifiers and counters all integrated on a single chip. The anodes are fabricated on the surface of the chip over a thick dielectric film. The active anode array... View full abstract»

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  • Comparative performance limits of MOSFET, MESFET and MODFET digital circuits

    Publication Year: 1990, Page(s):18.8/1 - 18.8/4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB)

    Using the static transfer curves derived from analytical drain current and threshold voltage models for short-channel MOSFETs, MESFETs and MODFETs, the FET scaling limits in CMOS and E/D MOSFET (NMOS), MESFET, and MODFET DCFL digital circuits are determined as 0.025 mu m, 0.05 mu m, 0.075 mu m, and 0.075 mu m (respectively) from noise margin considerations. The corresponding delay times of ring os... View full abstract»

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  • Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (Cat. No.90CH2860-5)

    Publication Year: 1990
    Request permission for commercial reuse | |PDF file iconPDF (1232 KB)
    Freely Available from IEEE
  • An interactive/automatic floor planner for hierarchically designed cell based VLSIs

    Publication Year: 1990, Page(s):30.4/1 - 30.4/4
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (336 KB)

    A floor planner suitable for hierarchically designed cell-based VLSIs to achieve an optimum layout design is described. The proposed floor planner has two novel features: the first is the combination of both manual manipulation in floor planning and automatic floor planning in order to make the best use of each method, considering the interdependence of these two methods. The second is the introdu... View full abstract»

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  • High speed 0.55 micron BiCMOS family of ASICs

    Publication Year: 1990, Page(s):16.2/1 - 16.2/4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    A BiCMOS family of ASICs with 290 ps delay, 0.55 μm Leff N (channel), complexity of 120000 to 200000 equivalent used gates, TTL/CMOS/ECL interface, up to 72 mA output drive capability, and multiport RAMs and ROMs is described. The trade-offs between CMOS and BiCMOS are discussed. The three different methodologies, cell-based, array-based, and embedded array, are compared. The featur... View full abstract»

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  • A knowledge based simulation environment

    Publication Year: 1990, Page(s):10.6/1 - 10.6/4
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    A knowledge-based shell for simulators has been developed as one part of a design environment for analog circuits. This shell offers circuit-specific simulation support exploiting expert knowledge for dealing with problems like test function generation and simulation clustering. Applications areas are all domains that require automated circuit characterization, such as synthesis or cell library ma... View full abstract»

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  • Hierarchical symbolic design methodology for large-scale datapaths

    Publication Year: 1990, Page(s):30.3/1 - 30.3/4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A hierarchical symbolic layout methodology for designing large-scale datapaths is proposed. The methodology constructs a datapath hierarchically by taking note of the bit-slice regular structure. It gives a globally optimized layout with a rapid optimizing loop. This approach has reduced design effort to 1/10 compared with conventional handcraft design (maintaining equivalent layout quality) for a... View full abstract»

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  • IDSIM2: an environment for mixed-mode simulation

    Publication Year: 1990, Page(s):5.2/1 - 5.2/4
    Cited by:  Papers (4)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    IDSIM2, an integrated computer-aided VLSI design verification environment in which several types of simulation tools share a common hierarchical circuit database is described. IDSIM2 performs a mixed fast-timing/circuit simulation and supports a parallel processing feature. Several feedback processing methods are also available. Results demonstrate a speedup of up to 1000 times over conventional c... View full abstract»

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  • SYMCELL-a symbolic standard cell design system

    Publication Year: 1990, Page(s):16.1/1 - 16.1/5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (536 KB)

    SYMCELL is a standard cell system that enables cells to be created, placed, and globally routed symbolically. Cell rows are compacted and pitchmatched, and channels are routed for a specific set of design rules. The symbolic cell libraries can be maintained independent of the process design rules, and new cells can be designed with the ease of symbolic layout. Circuit speed and layout density appr... View full abstract»

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  • A technical strategy for mixed analog-digital customs

    Publication Year: 1990, Page(s):10.5/1 - 10.5/4
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (688 KB)

    Three key system designers' requirements for custom mixed analog-digital ICs are identified, and strategies for meeting them involving process, simulation, and cell libraries are given. Examples of circuits using a suitable process and cell library are shown. A complex data acquisition system implemented using (a) standard components and (b) two mixed analog-digital custom ICs is illustrated. The ... View full abstract»

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  • STAT: a schematic to artwork translator for custom analog cells

    Publication Year: 1990, Page(s):30.2/1 - 30.2/4
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (208 KB)

    STAT (schematic to artwork translator) is a program to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology. The circuit designer first annotates the schematic with component matching and symmetric relationships. Software subroutines are used to generate and/or identify device artwork. Related component groups are placed first, so annotated layout c... View full abstract»

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  • Defect analysis and test generation for gate oxide shorts in CMOS ICs

    Publication Year: 1990, Page(s):28.6/1 - 28.6/4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    A test pattern generation algorithm for testing each type of gate to detect gate oxide short defects (605 in all) of the transistors composing it is presented. It is concluded that only the preceding logic is important as far as test generation is concerned, because it involves application of a test vector so as to provide a path from Vdd to ground through the gate of the transistor und... View full abstract»

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  • A new approach to event-driven analog/digital simulation

    Publication Year: 1990, Page(s):5.1/1 - 5.1/5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    SPECTRUM, an event-driven, mixed-signal, circuit simulation program, is discussed. By integrating high-level behavioral modeling and dynamic partitioning techniques, SPECTRUM is able to simulate complex digital/analog circuits accurately while taking maximal advantage of circuit latency. The current version of SPECTRUM uses a simple fixed-step integration algorithm. Multirate integration technique... View full abstract»

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  • A 300 K-circuit ASIC logic family CAD system

    Publication Year: 1990, Page(s):10.4/1 - 10.4/5
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent ... View full abstract»

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  • Multilayer area routing algorithm as an optimization problem

    Publication Year: 1990, Page(s):27.4/1 - 27.4/4
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A highly flexible, multilayer area router is presented. Routing is viewed as an optimization problem with constraints. A set of novel concepts are presented to minimize the cost (including the ability to get out of local minima), where the cost is the shorts (overlaps) between routes and zero cost implies clean routes. This router has been used successfully in high-density processor layouts, which... View full abstract»

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  • A CMOS VLSI chess microprocessor

    Publication Year: 1990, Page(s):15.3/1 - 15.3/4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    The Berkeley Chess Microprocessor (BCM) is a 200000 transistor, 1.2 micron CMOS (N-Well) die, 11 mm by 9 mm in area. It can generate three million legal moves/s. The BCM's novel architecture allows for evaluation of chess board positions several ply deep from the current board position. This chip has three evaluation innovations: (1) pins and X-ray attacks can be determined, (2) dynamic evaluation... View full abstract»

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  • An interactive graphical approach to module generator development

    Publication Year: 1990, Page(s):30.1/1 - 30.1/5
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    A design-by-example methodology is applied to a library of highly parameterized design-rule-independent SSI/MSI module generators. This graphical approach is far more intuitive than working procedurally. It reduces the software expertise required to develop generators, and reduces the generator development effort by 50%. In addition, generators can be modified and debugged graphically, greatly red... View full abstract»

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  • A universal test sequence for CMOS scan registers

    Publication Year: 1990, Page(s):28.5/1 - 28.5/4
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (412 KB)

    A systematic method for analyzing all possible faults within the scan path of a scan-based CMOS circuit is given. The analysis shows that both logic and current monitoring are necessary in order to detect all irredundant faults. A universal test sequence is derived based on the analysis of single bridging faults. This sequence also detects all irredundant stuck-at and stuck-open faults. SPICE simu... View full abstract»

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  • Efficient on-chip delay estimation for leaky models of multiple-source nets

    Publication Year: 1990, Page(s):9.6/1 - 9.6/4
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB)

    An algorithm for efficiently computing an Elmore approximation in a leaky RC tree which may contain any number of uniformly distributed RC segments is presented. This algorithm works in the frequency domain, and it owes much of its efficiency to the fact that intermediate results leftover from computation of the driving-point admittance approximation are reused. The algorithm for... View full abstract»

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  • Pole-zero simulator with component sensitivity analysis function

    Publication Year: 1990, Page(s):8.7/1 - 8.7/4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (280 KB)

    A pole-zero simulator with a component sensitivity analysis function has been developed in order to achieve high-performance characteristics in analog circuits. The functions of this simulator include specifying the circuit components which determine pole-zero values and intensity computation for the influence of individual components on such circuit characteristics as DC-gain, unity-gain frequenc... View full abstract»

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  • A 150 K-circuit ASIC family using a DRAM technology

    Publication Year: 1990, Page(s):4.6/1 - 4.6/5
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    The features of a gate-array ASIC family using a CMOS DRAM technology are described. The availability of DRAM, the mix of gate-array and standard-cell circuits, and the choice of using either DLM (double-level metal) or TLM (triple-level metal) provide a designer with options not available in other ASIC families. The associated design system enables design entry, physical design, design verificati... View full abstract»

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  • Behavioral analog circuit models for multiple simulation environments

    Publication Year: 1990, Page(s):5.5/1 - 5.5/4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (252 KB)

    A method for modeling analog circuits at the behavioral level using nonlinear differential equations is described. The resulting models execute efficiently in various simulation environments, including a circuit analysis program and an event-driven logic simulator. Behavioral models are expressed as differential equations with respect to time. A variety of linear and nonlinear operators are provid... View full abstract»

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  • A dynamically tracking clock distribution chip with skew control

    Publication Year: 1990, Page(s):15.6/1 - 15.6/4
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (392 KB)

    A novel single-chip clock distribution circuit is described. This circuit is a self-calibrating synchronization system that receives a periodic, digital clock signal as a reference and generates multiple system clock signals that dynamically track and are synchronized to the reference clock across temperature, voltage, and process variations. This chip is used as an integral part of the clock dist... View full abstract»

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  • A mixed level simulator mega-FAL with novel data structure oriented to HDL statements

    Publication Year: 1990, Page(s):10.3/1 - 10.3/4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    The VLCAD functional design subsystem, which consists of a mixed-level simulator, a logic synthesizer, and a functional test generation assistant, has been developed as a solution to the problem of reduction of design time in VLSI design. Application of the VLCAD to many VLSI products showed that it reduced the system design time by half. There is a need for a more efficient CAD system in order to... View full abstract»

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