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Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Date 13-16 May 1990

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Displaying Results 1 - 25 of 168
  • A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

    Page(s): 4.4/1 - 4.4/4
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    The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface. The gate array is fabricated using ASPECT-II (advanced single poly emitter coupled technology) with silicided polysilicon local interconnect and four-level metallization.<> View full abstract»

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  • Comparative performance limits of MOSFET, MESFET and MODFET digital circuits

    Page(s): 18.8/1 - 18.8/4
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    Using the static transfer curves derived from analytical drain current and threshold voltage models for short-channel MOSFETs, MESFETs and MODFETs, the FET scaling limits in CMOS and E/D MOSFET (NMOS), MESFET, and MODFET DCFL digital circuits are determined as 0.025 mu m, 0.05 mu m, 0.075 mu m, and 0.075 mu m (respectively) from noise margin considerations. The corresponding delay times of ring oscillators using these minimum length devices are shown to be 6.37 ps, 5.07 ps. 2.44 ps and 2.61 ps, respectively.<> View full abstract»

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  • Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (Cat. No.90CH2860-5)

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    Freely Available from IEEE
  • A dynamic CMOS multiplier for analog neural network cells

    Page(s): 26.4/1 - 26.4/4
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    A strobed multiplier circuit for use in integrated neural network architectures is presented. The circuit, which can be fabricated in a standard CMOS analog process, performs the two-quadrant weighting of interconnect signals via exponential charge packets onto capacitive summing buses. SPICE simulations and MOSIS fabrication results are presented. The proposed design is simple in structure, uses no operational amplifiers for the actual multiplication function, uses no power in the static mode, and has been implemented in standard 2 μm analog CMOS processing View full abstract»

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  • Design of a 64×64 photo current multiplexer for use in astronomical applications

    Page(s): 7.4/1 - 7.4/4
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    An investigation into techniques for the realization of a two-dimensional, photo-current multiplexer for use in astronomical applications is described. The design of a device based on this work is then described. The multiplexer uses a gated readout structure and an addressable buffer scheme to integrate the photo-currents generated by a staring array of indium antimonide (InSb) IR photodiodes bump bonded directly to the multiplexer. Fabricated in a 3-μm CMOS technology, the device has been successfully bonded to a photodiode array, and evaluation results have been obtained at a temperature of 5 K View full abstract»

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  • A preprogrammed artificial neural network architecture in signal processing

    Page(s): 26.5/1 - 26.5/3
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    A mask-programmable artificial neural network (ANN) chip architecture, the tile-based ANN chip assembly, test and simulation results, and use it in signal processing systems are presented. The ANN chip architecture itself is a critical portion of the development. It is presented as a tool, in an abstract fashion, and the system design it makes possible and the process by which algorithms are converted to silicon (chip floorplan, tiling, etc.) are emphasized View full abstract»

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  • A complete audio decoder IC for US television stereo using serial arithmetic

    Page(s): 13.4/1 - 13.4/4
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    The Thomson Consumer Electronics (TCE) stereo IC is a mixed digital-analog IC which performs all audio signal processing tasks associated with Broadcast Television Systems Committee (BTSC) multichannel television sound (MTS) decoding. The TCE stereo IC uses a totally digital signal processing system to do all the audio processing tasks. These are performed using a novel, space-efficient, block structured serial arithmetic system called BRECFAST. Signal inputs are digitized by double integration sigma-delta A/D converters and audio outputs are derived from four error-feedback D/A converters. The IC gives superior audio separation and enhanced tone controls, but its key features are its lack of alignments and low cost. This work describes two aspects of the IC: the digital signal processing included in the design and the serial arithmetic system used to implement it View full abstract»

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  • A general purpose high speed equalizer

    Page(s): 25.6/1 - 25.6/4
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    The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, such as the European D2-MAC and HD-MAC transmission standards. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment. In addition to the cabled D2MAC environment, this circuit can be implemented in such applications such as HDTV (HDMAC via satellite transmission). Its frequency (up to 40.5 MHz) and its flexibility due to programmable parameters allow this chip to be integrated in a wide range of systems View full abstract»

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  • STAT: a schematic to artwork translator for custom analog cells

    Page(s): 30.2/1 - 30.2/4
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    STAT (schematic to artwork translator) is a program to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology. The circuit designer first annotates the schematic with component matching and symmetric relationships. Software subroutines are used to generate and/or identify device artwork. Related component groups are placed first, so annotated layout constraints are preserved. A novel placement method which recognizes that analog schematic topologies often reflect desirable layout configurations is proposed. A flexible cell-level router has been developed to complete the layout View full abstract»

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  • Design Assistant: an expert tool for ASIC design

    Page(s): 29.3/1 - 29.3/4
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    The Design Assistant is an expert tool used for high-level what-if considerations from the very early stages of a design up to the point where the design capture is complete. It works on a high-level structural representation of a design so that it can be used before any logic is captured, and it supports a real top-down design approach with a refinement mechanism. Its goal is to answer questions such as: How big will this circuit be? What will the power dissipation be? Will it fit on a gate-array? Which package should I use? Should the design use one or two chips? The tool, a collection of designers' expertise, has been built on the top of a Prolog expert system containing all the technical data and estimation rules and providing a powerful and flexible environment View full abstract»

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  • IRIS: a 20 MHz Image Recognition Integrated System

    Page(s): 17.6/1 - 17.6/4
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    A high-performance image-processing chip with an architecture optimized for pattern recognition is described. This is the first VLSI device which integrates a complete pattern recognition system on a single chip including line delay circuitry. The full custom 1.5 μm CMOS circuit contains 250000 transistors and operates at an image sampling rate of 20 MHz. The chip die size is 12.7 mm×11.5 mm and is packaged in a 144 pin ceramic PGA. The maximum clock speed is 20 MHz, and the chip dissipates a maximum of 1.5 W View full abstract»

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  • An active thin-film magnetic head with 60 MHz bandwidth and internal amplification of 58 dB

    Page(s): 7.2/1 - 7.2/4
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    An integrated circuit that realizes such a monolithic combination of a thin-film magnetic head with a preamplifier in bipolar technology is described. It yields recording densities up to 2000 fc/mm on a flexible disk by the head, and provides a read signal amplification of 58 dB by the semiconductor circuit (SCC). Thus, signal levels up to 100 mV are attainable, which is typically more than 100 times larger compared with conventional heads. The combination of the normally incompatible thin-film and bipolar technology was possible by an appropriate choice of processing steps and two protective layers which allow the application of the necessary thin-film processes after fabrication of the SCC View full abstract»

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  • Fully-integrated correlated tuning processor for continuous-time filters

    Page(s): 25.7/1 - 25.7/4
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    Measurement results on the correlated tuning loop (CTL), a novel tuning loop for continuous-time filters integrated in a 2 μm CMOS process are presented. Measured performance indicates that a second-order bandpass filter at 2.5 MHz and Q-factor of 10 can be tuned with an error in resonance frequency of only 0.2% and a gain error of only 1.1 dB. The prototype circuit, which measures 4.8 mm2, has been designed and optimized specifically to tune a second order bandpass filter at 10 MHz. The CTL approach, however, may be applied to any filter structure in which the attenuation specifications can be translated to specifications of real and imaginary parts of transfer functions View full abstract»

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  • Direct solution of performance constraints during placement

    Page(s): 27.2/1 - 27.2/4
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    A practical set of features for meeting the constraints of high performance designs during placement has been developed. The tool observes signal path constraints in units of time, automatically trading off delay between nets on the critical paths. The tool can observe net constraints in units of delay or capacitance. These features are based on a fast and accurate algorithm for net wiring estimation. Using a constraints method enables the true timing problem to be solved better and eliminates design iteration. Additional features specific to ECL design are also available. Results show a 52% reduction in interconnect delay versus an unconstrained placement on the first test case View full abstract»

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  • A full 1.2 μm CMOS ECL-CMOS-ECL converter with subnanosecond settling times

    Page(s): 11.4/1 - 11.4/4
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    A full 1.2 μm CMOS circuit which converts digital signals from ECL to CMOS and vice versa is presented. High performances are obtained due to the use of only NMOS devices in the signal path, replica biasing for accurate control of the signal levels, and charge injection to ensure extremely steep edges and subnanosecond settling times. To test and demonstrate the possibilities, a full CMOS ECL-compatible repeater for a broadband ISDN switching board has been designed: the attenuated ECL signal is converted in CMOS levels, stored in a high-speed CMOS flip-flop (which represented CMOS logic), and finally converted back into an ECL signal. The system can detect and drive 75 Ω interconnected lines as long as 15 m. The total system has two clock slices (clock and clock inverse), four data slices and one frame slice View full abstract»

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  • Implementation of a neuron dedicated to Kohonen maps with learning capabilities

    Page(s): 26.1/1 - 26.1/4
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    A compact implementation of Kohonen-oriented neurons with learning capability, using both analog and digital techniques, with standard low-cost CMOS technologies, is described. Each synaptic weight is stored as a discrete voltage on a capacitor. Leakage currents are compensated by a special circuitry, which is also used for learning. Input signals are frequency-coded pulse streams, and the synaptic multipliers are reduced to simple AND gates View full abstract»

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  • ASIC vision

    Page(s): 7.3/1 - 7.3/4
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    Advances in VLSI vision sensor design that enable high-quality, analog images to be formed through devices fabricated using standard 5 V CMOS ASIC processes are reported. The potential for integrating mixed sensor-processor systems, using an integrated VLSI camera system as an example, is reported. The feasibility of the techniques is confirmed by results obtained from working prototype CMOS sensor arrays. It is believed that the methods and results demonstrated can form the basis of a first generation of cost-effective ASIC vision products View full abstract»

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  • A reconfigurable content addressable memory

    Page(s): 24.1/1 - 24.1/4
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    A 256 word by 64 b reconfigurable content addressable memory (RCAM) that can be written, searched, or read with a 100 ns cycle time is described. Designed for general high-speed table lookup applications, the RCAM has self-test and reconfiguration features to simplify testing and improve yield. For more than 256 words, the RCAM has extension logic built into the word-finding logic. In a multichip application, all pins of each RCAM are tied together, except for the F-line pins (Fi, Fo, and Fd). The F pins ensure that only one chip writes onto the data bus and only one chip stores a word. The Fi, Fo, and Fd are analogous to the carry in, carry propagate, and carry generate signals of a carry look ahead adder View full abstract»

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  • A maze routing method of combined unity and infinity expansion distances

    Page(s): 27.3/1 - 27.3/4
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    A method for maze routing problems which combines unity and infinity distances into the wavefront expansion phase of a generic Lee's algorithm is described. A unity distance wavefront is maintained at each step of the expansion to guarantee finding minimum-length paths, while an infinity distance labeling scheme is adapted to ensure that the labels can be used to determine a minimum-corner path among them. Since the originally proposed three sequential expansions are replaced by a single one, the routing time is significantly improved View full abstract»

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  • An opto-electronic Viterbi traceback processor for decoding convolutional codes

    Page(s): 13.7/1 - 13.7/4
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    The design, circuits, and layout of the Viterbi traceback processor (VTP), a full-custom ASIC utilizing optical, analog, and digital circuits, are presented, The VTP subsystem, when combined with a holographic (optical) metric generation subsystem, is designed to implement the Viterbi decoding algorithm. The prototype chip, 6900×6800 μm2 was designed to decode convolutionally encoded data from a rate=1/2, K=5 encoder and is comprised of 2k photoreceptors, 2k-1 comparators, a 2K-1×16 array of 2-input multiplexor/shift register cells, and two sizes of clock buffer/driver circuits. Two scan-path chains have been designed in for testability View full abstract»

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  • A 20 MHz QAM chip with numerical controlled carrier generator for research in HDTV

    Page(s): 25.1/1 - 25.1/6
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    The implementation of a digital quadrature amplitude modulator/synchronous demodulator with numerical controlled carrier generator for research on high-definition television applications is described. The chip will handle clock rates up to 20 MHz and provide carrier frequencies from 3.0 Hz to 10 MHz in 3 Hz increments using a numerical controlled oscillator (carrier generator). In addition, a +/-360 degree phase shift capability in 0.03 degree increments is also provided. The methodology used to construct this system is a standard cell library using a 1.5 μm CMOS process. Further enhancements on the chip are two compiled ROMs, two 8×8 Booth multipliers, and two FIR notch filters View full abstract»

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  • The WASP 2 WSI massively parallel processor demonstrators

    Page(s): 17.1/1 - 17.1/4
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    WASP 1 is reviewed, and the WASP 2a and WASP 2b wafer-scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology, are discussed. These latter devices are defect-tolerant arrays of 864 and 6048 processing elements and integrate 1.26 M transistors (4 cm×4 cm) and 7.87 M transistors (10 cm×10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed at Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI program View full abstract»

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  • An integrated system for circuit level hot-carrier evaluation

    Page(s): 19.4/1 - 19.4/4
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    An integrated system designed to evaluate and predict hot-carrier effects at the circuit level is described. The system will perform device stress, collect data, extract parameters, and simulate circuit aging behavior using the circuit aging simulator from UC Berkeley. Enhancements made to the device-stress and data-analysis portions of the system were found necessary to achieve accurate circuit reliability prediction. Less than 2% error is observed between the measured and simulated performance of a 0.5 μm ring oscillator test circuit View full abstract»

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  • CMOS amplifiers incorporating a novel slew rate enhancement technique

    Page(s): 11.6/1 - 11.6/5
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    A novel technique for enhancing the slew rate in CMOS amplifiers is described. The enhancement is provided by an auxiliary circuit which is automatically activated during transients. The main amplifier is not stressed with large currents, thus minimizing power dissipation and avoiding signal swing problems. This technique is quite generic, and can be applied to a variety of amplifier structures. An experimental operational transconductance amplifier incorporating this technique has been fabricated. A slew rate of 1 V/μs with a 10000 pF load capacitance has been achieved, while requiring a quiescent power dissipation of less than 1.5 mW View full abstract»

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  • SVP: serial video processor

    Page(s): 17.3/1 - 17.3/4
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    Real-time video signal processing is achieved by a serial video processor (SVP) which inputs/outputs video signals serially and processes the data in parallel during each horizontal line period. This work describes the architecture of the SVP. An overview of the device, unique design techniques, and test methodology are given. Two SVPs applied to digital color TV image processing are discussed. Specifically, this is an Improved Definition TV application providing motion-adaptive digital Y/C separation, noise reduction, and progressive scanning. The addition of multiplexers in the appropriate data paths allows this same basic circuit to perform special features (still, strobe, zoom, picture-in-picture, multiscreen, etc.) View full abstract»

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