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High Performance Applications of Parallel Architectures, IEE Colloquium on

Date 1 Feb 1994

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Displaying Results 1 - 11 of 11
  • A programmable-logic based multiprocessor engine for real-time vision preprocessing

    Publication Year: 1994 , Page(s): 3/1 - 3/6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    Real-time vision is central to many embedded applications (e.g. vehicle guidance). It is a computationally intensive task well beyond current general purpose computing platforms such as PCs and workstations. Thus, most real time vision systems need special high performance computing platforms, commonly provided in the form of parallel processing engines or dedicated hardware. The proposed architecture uses new generations of re-programmable logic devices and modularised hardware, thereby gaining the performance advantage of hard-wired logic with the flexibility and associated economies of programmable systems. The architecture takes the form of an extensive processing hierarchy consisting of a set of tightly coupled parallel processors, each processing a portion of the image using a classic pipeline arrangement. A programmable image splitting (and reconstruction) engine feeds this array and offers the potential of further enhancing the performance of the engines by restructuring the pixel distribution (bit-shuffling) so as to match the requirements of the executing algorithms. The physical implementation will be based on a modularised bus system together with EPLD processing devices. The authors report on the predicted performance of low level vision functions running on this architecture View full abstract»

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  • On applying parallel processing in advanced control of induction motor drives

    Publication Year: 1994 , Page(s): 7/1 - 7/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Parallel processing offers realistic solutions to implement cost-effectively modern electrical drive systems comprising such advanced features as real-time control, online diagnostics and auto-tuning of system parameters. The implementation complexity of parallel processing by conventional multi-processor systems however has seldom been addressed and adequately documented. The proposed drive system serves to evaluate the impact of parallel processing on motor drive control applications, when effort can be turned away from low-level implementation as a result of emergence of some dedicated parallel processors. Some salient features of the drive system include real-time generation of pulse-width modulated (PWM) waveforms, programmable soft-starting, online user input for PWM parameters, dynamic braking and open loop vector control View full abstract»

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  • Animation using accelerated ray tracing on a hypercube

    Publication Year: 1994 , Page(s): 2/1 - 2/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    Ray-tracing is an image synthesis method producing some of the most photorealistic images to date. The method is taken from classical optics, where rays of light are traced around a scene inside the computer and results are plotted into the resulting image. This simple technique enables refraction, reflection and shadowing to be created in the same algorithm. The drawback, however, is that the method is very computationally expensive, and hence requires accelerating to enable images to be produced in a reasonable time. Most of the time spent in any ray-tracing algorithm is spent in ray-object intersection tests, so techniques to accelerate the ray tracing process have concentrated on this problem. Two acceleration techniques are investigated, those of parallelism and temporal coherence View full abstract»

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  • A 1-Gflop triangular pseudo-systolic processor

    Publication Year: 1994 , Page(s): 6/1 - 610
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    Modern signal processing often requires arithmetically intensive algorithms. The complexity of such algorithms and their development of `batch processing' solutions does not, in general, provide the bandwidth or convenience required for processing signals in real-time at rates greater than a few hertz; a different approach is needed. J.G. McWhirter and T.J. Shepherd (1987) proposed a systolic architecture which provided the basis for an efficient `flow-through' processing technique and much effort has since been devoted to the development of suitable algorithms. In particular, signal processing techniques which make use of a least-squares optimisation are often used in signal processing strategies. It was shown by McWhirter and Shepherd that the QR algorithm, used for least-squares optimisation, could be expressed in a form suited to a triangular systolic array. However, the number of systolic nodes and hence processors, in an array capable of optimising a problem with 81 unknowns, for example, would be 3321; such an array would be large and expensive. An intermediate and economically attractive alternative is to use substantially fewer processors emulating the same flow-through architecture whilst providing sufficient bandwidth; a `pseudo-systolic' solution. Using this approach a group of nodes would share a processor View full abstract»

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  • Design and application of parallel digital signal processor based image processing system for industrial inspection

    Publication Year: 1994 , Page(s): 4/1 - 4/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    The use of computer-based inspection systems in industrial environments is becoming more common due to the fact that they produce consistent results compared to traditional methods of inspection. In certain manufacturing applications, the inspection of the product may become a bottleneck. This is caused by the large amount of data that has to be processed in conjunction with high computational requirements. In order to deliver the desired throughput rates required typically necessitates the use of specialised hardware. The Coherent and Electro-optics Research Group at LJMU currently has several inspection applications which require computational rates considerably higher than can be achieved using commodity systems. A parallel digital signal processor (DSP) based image processing system is being developed which will resolve the current computational deficiency View full abstract»

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  • A transputer-based parallel DSP environment

    Publication Year: 1994 , Page(s): 8/1 - 8/6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The traditional DSP design and development environment is generally based on the use of a single processor and suffers from a number of limitations including the following: a time-consuming design cycle from specification to the final product development; dependence on hardware and hence lack of portability to different DSP platforms; lack of exploitation of algorithmic and architectural parallelism for DSP design. The authors present a multiprocessor environment, called Taurus, for design and development of DSP algorithms and applications. The important features of such environment are introduced, and typical experimental results using an ADPCM system are presented and discussed View full abstract»

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  • SPARC-GAP: a parallel genetic algorithm processing platform

    Publication Year: 1994 , Page(s): 5/1 - 5/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    Genetic algorithms (GA) have emerged as a powerful technique for solving NP-complete problems, most notably those requiring optimisation of a system within a given set of constraints. The authors propose a novel attempt to realise a relatively low-cost parallel processing platform hosted on a Sun workstation that will enable unimpeded exploration of genetic algorithms. The system will be implemented on the SPARC-GAP platform View full abstract»

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  • IEE Colloquium on `High Performance Applications of Parallel Architectures' (Digest No.1994/026)

    Publication Year: 1994
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (16 KB)  

    The following topics were dealt with: parallel implementation of pattern classification; accelerated ray tracing on hypercube; programmable logic based multiprocessor for vision preprocessing; parallel digital signal processor parallel genetic algorithm processing; triangular pseudo-systolic processor; parallel processing for induction motor drive control; and parallel processing for real-time control View full abstract»

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  • Parallel architectures for real-time control

    Publication Year: 1994 , Page(s): 9/1 - 9/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    The authors present an investigation into the utilisation of parallel computing techinques for real-time simulation and control of a flexible beam structure in transverse vibration. The performance demands of modern control systems require the employment of complex algorithms with demanding operations which, in turn, leads to shorter sampling times. Therefore, real-time performance in control applications where the use of advanced control methods is warranted becomes difficult to accomplish. Many demanding complex control processes cannot be satisfactorily realised with conventional uni-processor and multi-processor systems. Previous investigations have demonstrated the limitations of employing only transputers for real-time implementations in control applications. Alternative strategies where multi-processor based systems are employed, utilising digital signal processing (DSP) and parallel processing techniques, could provide suitable methodologies View full abstract»

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  • Parallel processing for real-time adaptive robot control: theoretical issues and practical implementation

    Publication Year: 1994 , Page(s): 10/1 - 10/2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    The authors present a practical solution to the problem of real-time robot control including the nonlinear dynamic model of the manipulator by employing a parallel processing approach. The parallelism inherent in the adaptive controllers is exploited to obtain an efficient implementation that reduces the overall computation time to within the limit acceptable for real-time control. The distributed algorithm is implemented on a network of transputers for the six-joint PUMA 560 arm View full abstract»

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  • Parallel implementation of pyramidal classifier structures for high performance pattern recognition applications

    Publication Year: 1994 , Page(s): 1/1 - 1/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    The authors address a number of important issues related to the specification and implementation of high performance algorithms for pattern classification. In particular, performance is optimised by efficient implementation using a parallel processing computational infrastructure and the specification of techniques which allow the opportunity for an effective pattern rejection mechanism and a means for decision making at the earliest stage in the processing chain consistent with avoiding degradation of recognition performance. The techniques proposed are general purpose and may be applied to hierarchical pyramidal structures of any order View full abstract»

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