IEE Colloquium on Synthesis and Optimisation of Logic Systems

14 Mar 1994

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  • IEE Colloquium on `Syntheses and Optimisation of Logic Systems' (Digest No.1994/066)

    Publication Year: 1994
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (24 KB)

    The following topics were dealt with: mixed representations; multi-level optimisation; VLSI; logic gates; minimum-size implementations; PLAs; simulated annealing; behavioural descriptions; fuzzy logic; and asynchronous controllers View full abstract»

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  • Logic synthesis using both inclusive-OR and exclusive-OR sums of products

    Publication Year: 1994, Page(s):1/1 - 1/6
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (320 KB)

    Presents work aimed to create an interactive logic synthesis system using both inclusive-OR and exclusive-OR sums of products to synthesize switching functions. As a basis of the new package an existing multi-level logic synthesis system SIS was chosen. This system supports the inclusive-OR sum of products representation, and the main idea behind the work is to supply the system with functions sup... View full abstract»

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  • Logic realization using mixed representations based on Reed-Muller forms

    Publication Year: 1994, Page(s):2/1 - 2/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (236 KB)

    Logic design using Boolean representations employs a complete gate set. The conventional Reed-Muller representation only uses INVERTER, AND and XOR gates. This means that the conventional Reed-Muller form, in a sense, is less flexible and doesn't always generate economical circuits. This paper discusses some useful properties of Reed-Muller forms, and the use of mixed representations based on Reed... View full abstract»

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  • Multi-level optimisation of fixed polarity Reed-Muller expansions using Reed-Muller binary decision diagrams

    Publication Year: 1994, Page(s):3/1 - 3/4
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (292 KB)

    The Reed-Muller binary decision diagram (RMBDD) is an alternative way of representing generalised Reed-Muller (GRM) expansions. This graphical representation provides a complete canonical description of GRM functions and is a counterpart of the well-known Boolean binary decision diagram. The structure of RMBDDs and rules for reducing the size of the diagrams are described in this paper; additional... View full abstract»

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  • Using redundant number representations for efficient VLSI implementation of modular arithmetic

    Publication Year: 1994, Page(s):4/1 - 4/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (196 KB)

    The VLSI implementation of multiplication is usually achieved as an addition of partial products. Recent research has proposed the use of redundant number representations (RNR) to limit the carry propagation inherent within these additions, enabling high-speed multiplier designs. Multiplication over a modulus is often accomplished by interleaving the partial product additions with a modular adjust... View full abstract»

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  • Fredkin gates as a basis for comparison of different logic design solutions

    Publication Year: 1994, Page(s):5/1 - 5/4
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (208 KB)

    In this paper one particular gate is proposed which has the potential to be implemented optically. It has the advantage that, if necessary, it can perform conventional Boolean logic, but it can also perform alternative logics such as conservative logic, multi-valued logic and threshold logic. Since the same gate is used regardless of the logic, it is possible to make a comparison of the various lo... View full abstract»

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  • Synthesis of self-clocked asynchronous controllers

    Publication Year: 1994, Page(s):11/1 - 11/5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (360 KB)

    The contribution of this paper is a novel and systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding. Multiple input changes are allowed. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. It avoids extra delay elements often necessary in self-c... View full abstract»

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  • Simulated annealing for folding of programmable logic arrays

    Publication Year: 1994, Page(s):7/1 - 7/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (276 KB)

    Addresses the multiple column folding using a methodology using the SA algorithm. First of all, the multiple unconstrained column folding is studied. Then the SA algorithm for solving several constrained folding problems is used and the simple folding is considered as a special case of a constrained folding View full abstract»

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  • A design methodology for fuzzy logic controllers

    Publication Year: 1994, Page(s):10/1 - 10/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (204 KB)

    Fuelled mainly by developments in Japan, there is currently a resurgence of interest in the application of fuzzy logic controllers (FLCs). The rapid advances in digital systems, particularly in microprocessors and VLSI, and the huge increase in potential applications areas, has brought design methods for such systems to the forefront. This paper, by reviewing the basic theory of fuzzy logic, devel... View full abstract»

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  • Partitioning logic functions for minimum size implementations

    Publication Year: 1994, Page(s):6/1 - 6/8
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (360 KB)

    When implementing large logic functions there is a need to partition the function to fit the implementation primitives. There is, at present, no simple analytic method of achieving a `best' implementation. In this paper, classical decomposition theory is extended to allow the analysis of functions with large input fields and multiple outputs, specified by their ON-terms and including `don't-care' ... View full abstract»

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  • Operation scheduling in VLSI circuit design

    Publication Year: 1994, Page(s):9/1 - 9/5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (248 KB)

    The crucial step involved in the transforming of a behavioral specification given at the algorithmic level into a RTL structure (high-level synthesis) is the operation scheduling, which basically is the task of defining the timing of the operation execution. A new algorithm solving the scheduling problem is presented and compared with the best ones published. The scheduling algorithm is integrated... View full abstract»

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  • Design of complex systems from behavioural descriptions using formal methods

    Publication Year: 1994, Page(s):8/1 - 8/4
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (264 KB)

    The computer aided simulation system CASSY is a new CAD tool that supports particularly the early design stages of mixed digital and analog signal processing systems from behavioural descriptions in an interactive way by fast simulation. Existing simulation systems mostly work on a numerical basis, thus requiring much computing time. In contrast, the CASSY System operates at a high level of abstra... View full abstract»

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