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Design and Application of Parallel Digital Processors, 1988., International Specialist Seminar on the

Date 11-15 Apr 1988

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Displaying Results 1 - 25 of 35
  • SUPRENUM: a massively-parallel machine for numerical applications

    Publication Year: 1988, Page(s):163 - 171
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (656 KB)

    A detailed discussion of the hardware and software architecture of the SUPRENUM supercomputer is presented. A largely bottleneck-free interconnection structure is accomplished in a hierarchical manner: the machine consists of up to 16 `clusters', and each cluster consists of 16 `working nodes' plus some organizational nodes. The node is accommodated on a single circuit board; its architecture is b... View full abstract»

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  • Neural network computation

    Publication Year: 1988, Page(s):160 - 162
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (220 KB)

    Since 1982 there has been an enormous resurgence of interest in the possibility of making trainable, general purpose pattern recognition machines which are intended to mimic some of the processing abilities of human brains. A neural network `computer' consists of a set of processing units (or artificial neurons) joined together by a set of weighted connections. Such networks are programmed by appl... View full abstract»

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  • Concurrency and communication in Delta Prolog

    Publication Year: 1988, Page(s):94 - 104
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (932 KB)

    Describes and exemplifies the logic programming language Delta Prolog, an extension to Prolog to include AND-concurrency and interprocess communication. Besides its declarative semantics, its operational semantics, comprising distributed backtracking, is especially emphasized. The extension is obtained, at the language level, by introducing three additional goal types: splits, events, and choices.... View full abstract»

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  • Replacing hardware that thinks (especially about parallelism) with a very smart compiler

    Publication Year: 1988, Page(s):153 - 159
    Cited by:  Papers (2)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (544 KB)

    There is a tradeoff that touches many areas of computing: doing work at run time, usually in the hardware, vs. doing work in software at compile time. This tradeoff exists in some very visible and other not as visible places in any computer system. One surprising place in which it has a large effect is in the specification of fine-grained parallelism. The author examines that tradeoff, particularl... View full abstract»

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  • Parallel processing-parallel thinking-the needs of a National Strategy

    Publication Year: 1988, Page(s):202 - 203
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (116 KB)

    There are three possible solutions to satisfy the demands for increased computing performance: increased MICRO miniaturisation could, theoretically, enable von Neumann machines to be constructed in smaller and smaller physical volumes that would enable the frequency/wavelength dichotomy to be controlled; a space-time computing machine could be designed that takes account of the fundamental physics... View full abstract»

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  • Design by calculation and proof

    Publication Year: 1988, Page(s):87 - 93
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (432 KB)

    Expounds a philosophy of engineering design which is stimulated, guided and checked by mathematical calculations and proofs. The philosophy is illustrated by a familiar example, the design of a hardware circuit for addition of natural numbers in binary representation View full abstract»

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  • On new generation dataflow architecture

    Publication Year: 1988, Page(s):112 - 115
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (220 KB)

    Dataflow machines execute instructions only when the operands are available. Therefore each execution of instructions are treated as an independent event and exploitation of maximum concurrency at a scalar level, vector level, and function level is achieved. The author describes the architecture of a dataflow supercomputer, SIGMA-1, developed over several years. Since the SIGMA-1 system forms a pi... View full abstract»

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  • A loosely coupled parallel LISP execution system

    Publication Year: 1988, Page(s):128 - 133
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    There are many ways in which it is possible to start the quest for parallelism in a computing system. The work described in this paper started from a number of clear criteria which have shaped the whole project. These are presented and explained in the first section, and this leads directly to the hardware environment. The software environment forms the subject of the second section. There are a n... View full abstract»

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  • The Computing Surface

    Publication Year: 1988, Page(s):139 - 142
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (336 KB)

    The Computing Surface is a flexible, extensible computing system which is constructed from a choice of intelligent building blocks. A variety of building blocks are available with a range of computational or peripheral capabilities View full abstract»

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  • Systolic arrays for high throughput front-end signal processing

    Publication Year: 1988, Page(s):148 - 152
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (328 KB)

    After reviewing the requirement for and form of systolic arrays for front-end processing, the author discusses work that has led to the construction of such an array in order to demonstrate the use of these structures for adaptive beamforming. He concludes by considering the design of a very high performance integrated circuit (VHPIC) chip which will enable the implementation of high through-put f... View full abstract»

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  • Fractal graphics and image compression on a DAP

    Publication Year: 1988
    Cited by:  Patents (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (92 KB)

    The work of M. Barnsley and others at Georgia Institute of Technology, (Byte, P.215, January 1988) is producing dramatic results for high compressed graphics and images using Fractal based techniques for both movies and stills. Compression ratios of around 10000 to 1 are claimed. An important limitation is that both compression and regeneration are computationally intensive; Barnsley has mentioned... View full abstract»

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  • Language first philosophy [parallel computers]

    Publication Year: 1988, Page(s):83 - 86
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (316 KB)

    Parallel computers are an obvious way of providing increased computing power and utilizing the benefits of VLSI technology in a cost-effective manner. However, it is difficult to argue that parallel computing has been an unqualified success since the first serious attempts at real parallel structures some 20 years ago. The author argues that this can be attributed, to a large extent, to the concen... View full abstract»

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  • Parallel processing and database architectures

    Publication Year: 1988, Page(s):48 - 52
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (324 KB)

    A fundamental mismatch between programming tools and the nature of real hardware has been removed by the introduction of parallel processes to the model of computation. This is exemplified by the programming language occam (trade mark of the INMOS group of companies), which implements Communicating Sequential Processes (CSP) on INMOS transputers. The paper notes some of the characteristics of appl... View full abstract»

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  • Bit level pipelining of recursive computations

    Publication Year: 1988, Page(s):194 - 198
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (372 KB)

    Presents a novel solution to the problems of pipelining bit parallel recursive operations at bit level. A bit level first order IIR filter section is presented in which bit level pipelining is used to obtain a high throughput rate. These ideas are then extended and a simple bit level systolic building block is presented which can be used in the construction of a wide range of recursive filters. Th... View full abstract»

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  • PICAP 3. A coarse-grained linear SIMD-array

    Publication Year: 1988, Page(s):74 - 80
    Cited by:  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (364 KB)

    Gives a brief description of the overall architecture of PICAP 3. The redesigned processor module has full floating-point arithmetic so that a 32 module machine will have a peak performance of 320 MFLOP. The authors show how the linear organization and the local address modification can be used efficiently for algorithms like FFT. Transposition, Matrix multiplication, Histogramming, Convolution an... View full abstract»

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  • Chess on a hypercube

    Publication Year: 1988, Page(s):30 - 42
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (760 KB)

    The authors have developed a parallel chess program to run on distributed memory, multiple instruction stream computers. The program follows the strategy of currently successful sequential chess programs: searching of an alpha-beta pruned game tree, iterative deepening, transposition and history tables, specialized endgame evaluators, and so on. The search tree is decomposed onto a hypercube (an N... View full abstract»

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  • The Edinburgh Concurrent Supercomputer: project and applications

    Publication Year: 1988, Page(s):172 - 179
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (976 KB)

    The Edinburgh Concurrent Supercomputer (ECS) project is built around a Meiko Computing Surface, and offers a networked multi-user facility for academic, industrial and commercial applications. The authors describe first the background to the project, and the present status of funding, hardware and software. The facility has presently more than 100 registered users, the authors describe some of the... View full abstract»

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  • Software for parallel processing

    Publication Year: 1988, Page(s):105 - 111
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (592 KB)

    It is clear that effective parallel processing hardware is already being built now, while the field is at an early stage, and there will be major advances further increasing the potential of parallel processing hardware over the next decade. The problem for parallel processing is the software. The authors present the viewpoints on some approaches to effective parallel processing software View full abstract»

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  • Functional programming on the GRIP multiprocessor

    Publication Year: 1988, Page(s):116 - 127
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (764 KB)

    Most MIMD computer architectures can be classified as tightly-coupled or loosely-coupled, depending on the relative latencies seen by a processor accessing different parts of its address space. By adding microprogrammable functionality to the memory units, the authors have developed a MIMD computer architecture which explores the middle region of this spectrum. This has resulted in an unusual and ... View full abstract»

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  • Benchmarking parallel architectures

    Publication Year: 1988, Page(s):134 - 138
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (440 KB)

    In the developing world of parallel processing, there is a fundamental reason for benchmarking. The prime motivation for parallelism is better exploitation of VLSI technology and the role of benchmarking is wider than mere customer evaluation: it is needed to guide the improvement of parallel machines and the genesis of new parallel architectures. The author looks at the problems of benchmarking p... View full abstract»

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  • The effective use of SIMD processor arrays

    Publication Year: 1988, Page(s):143 - 147
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    Many computationally intensive problems have a very high degree of structured, fine-grain parallelism and benefit substantially from highly parallel execution. Such problems map efficiently on to truly parallel SIMD (Single Instruction stream, Multiple Data stream) processor arrays. This is essentially because the control, synchronisation and communication associated with the constituent parallel ... View full abstract»

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  • Applications of parallel processors in molecular biology

    Publication Year: 1988, Page(s):53 - 56
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (312 KB)

    Molecular biology analyses the molecular basis of living systems. The chemical complexity of biological systems of importance (e.g. enzyme action, organelle assembly, membrane transport, antigen-antibody reactions, cell recognition and many others) is at the extreme end of the range to which many physical methods of analysis can be applied. Developments will follow progress in the physical science... View full abstract»

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  • A linear algebra library for high performance computers

    Publication Year: 1988, Page(s):199 - 200
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (100 KB)

    Gives a brief description of a project to design and implement a transportable linear algebra library in Fortran 77 for efficient use on high-performance computers. The library will be based on the well-known and widely used packages EISPACK and LINPACK for solving eigenvalue problems and linear equation and linear least squares problems respectively. As with EISPACK and LINPACK, the library will ... View full abstract»

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  • Fault tolerant, self repairing transputer arrays

    Publication Year: 1988, Page(s):81 - 82
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (148 KB)

    The transputer is a device that has unique features making it suitable for both computationally intensive and fault tolerant applications. A particularly important features is that transputers have been designed as components of multi-processor systems. To operate in space, devices need to be resistant to radiation effects. Gamma particles have a cumulative effect which causes the power consumptio... View full abstract»

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  • A 3D vision system for robotics

    Publication Year: 1988, Page(s):43 - 47
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents an overview of the Sheffield AIVRU 3D vision system for robotics. The system currently supports model based object recognition and location; its potential for robotics applications is demonstrated by its guidance of a UMI robot arm in a pick and place task. The system is currently being developed to allow robot navigation by utilising visual feedback. The idea is to exploit the temporal c... View full abstract»

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