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Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Date 14-16 Feb. 1990

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Displaying Results 1 - 25 of 92
  • 1990 37th IEEE International Conference on Solid-State Circuits [front matter]

    Page(s): C1 - C3
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    Freely Available from IEEE
  • Table of contents

    Page(s): 4 - 7
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    Freely Available from IEEE
  • Supercomputers for the nineties: making the powerful accessible

    Page(s): 12 - 14
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    It is pointed out that providing access to the power of a supercomputer is the best way to foster supercomputer use. Accessibility has several dimensions. First, the system must provide a cost-effective solution to the problem. If the user determines that the computational cost is too high, the system is really not accessible. Secondly, many users want to submit larger problems without increased solution wait time. The system must provide connectivity. Thirdly, the cost of a classic supercomputer requires that in most cases users must share the resource. This normally places the system in a central location and adds the requirement of network access to the CPUs and to the file systems. Fourthly, the system must be reliable. Finally the user demands ease of use through familiar, friendly operating system software and intelligent compilers which automatically detect inherent problem parallelism and map it to the hardware.<> View full abstract»

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  • The new joint R&D

    Page(s): 16 - 19
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    It is pointed out that the era of collaboration among competitors has arrived. Virtually every vendor of semiconductor devices, equipment, and materials is engaged in at least one multicompany collaboration to develop processes, tools, and technologies. In 1982, when Microelectronics and Computer Technology Corporation (MCC) was founded, the prevailing view was that competitors cannot and should not share proprietary information, that their competitive habits overpower any collaborative desires, and that invention is fundamentally best undertaken by each company on its own. Today, that skepticism must confront the changes that have taken place in the world of industrial and academic research and development. The author provides examples of collaborative work, looks into the logic of joint research and development, and considers the design of R&D collaboratives, their secretariats, their operating entities, and their future.<> View full abstract»

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  • The present state of high definition television and its impact on solid state circuits

    Page(s): 20 - 23
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    The author points out that with rapid progress in technology and the availability of different media, such as satellites, fiber optics, and disks, television will change to enhance the viewing experience. Improvements will take place in spatial resolution, large screens in both home and theater, digital stereo, and surround sound. Throughout the world there is an enormous effort being expended on high-definition television (HDTV) involving all parts of the television chain, from production equipment, to transmission standards, to home display. A number of essential items have to be developed. Transmission is a more localized phenomenon, depending on the availability of satellites and unused spectrum in terrestrial networks and cable systems. Several approaches are being studied. The author discusses the development of HDTV production standards, as well as the need for new components and solid-state circuits. In particular, he considers the experience obtained with the HDMAC bandwidth reduction decoder (BRD).<> View full abstract»

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  • Mixed digital/analog signal processing for a single-chip 251Q U interface transceiver

    Page(s): 26 - 27
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    Careful partitioning of signal-processing tasks between the analog and digital domains to exploit the strengths of each results in an efficient design of a 2B1Q ISDN basic-rate U-interface single-chip transceiver. This 5-V CMOS device provides transmission across the digital subscriber line at 160 kb/s full duplex, in full compliance with ANSI standard T1.601. The serial 2B+D data from the digital interface is rate-adapted to 160 kb/s and cyclic redundancy check (CRC), maintenance, and control bits are inserted in the digital interface (DIF) section of the circuit. The resulting data stream is then scrambled and 18-b synchronization words are inserted. Conversion to an 80-kHz four-level signal takes place in the line encoder. The transmitter includes a 2B1Q pulse shaper, a five-level fully differential pulse-duration-modulation digital-to-analog (PDM D/A) converter, a third-order transmit filter, and a fully differential line driver. A raised-cosine 78% time-roll-off pulse is stored in the pulse shaper, using a PDM code, at 96 samples per baud. Pulse symmetry allows storage of the first half-pulse only. The back half is generated by a time-mirror circuit. At every baud interval, the current di-bit encodes the pulse front half, while the past di-bit encodes the pulse back half. The two resulting quantities are then combined and provided to a 7.68-MHz five-level PDM D/A converter. Undesirable high-frequency components are eliminated by one pole of low-pass filtering in the D/A converter circuit and two extra poles in the line drive circuit.<> View full abstract»

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  • A subscriber line interface processor for asynchronous transfer mode switching system

    Page(s): 28 - 29
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    A subscriber line interface processor (A-LIP), which connects a conventional analog telephone line to a port on an asynchronous transfer mode (ATM) switching network through the contention control circuit, has been developed. The functions and circuit structure of the A-LIP chip designed to enhance the efficiency of ATM transmission, a divider added to the digital signal processor in a pipeline processing environment, and a cell data addressing scheme for transferring data between memory and input/output buffers without interfering with pipeline processing are described.<> View full abstract»

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  • A 250 Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

    Page(s): 30 - 31
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    In the CMOS cross-point LSI described, fully synchronous switching capability for fixed-length ATM cells (packets), as well as the functions of conventional cross-point switches, has been realized. Packet broadcast capability has also been achieved as the result of input-oriented bit-map routing architecture. In order to exchange 32 packet links at the broadband line speed, tristate buffers and control latches with reduced parasitic capacitors have been utilized. The 40 k transistor chip is fabricated with a 1.0- mu m double-metal-layer n-well CMOS technology. The switch matrix is 2.4*3.2 mm. The chip size, 7.4*7.4 mm, is set by the 113 signal pads and the 39 voltage supply pads. Voltage supply nodes for output buffers are completely separated from the others. 250-Mb/s operation has been verified under nominal conditions with a 176-pin PGA package. Operating from a -4.5-V supply at 160 Mb/s, the chip dissipates 1.2 W.<> View full abstract»

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  • A CMOS Batcher and banyan chip set for B-ISDN

    Page(s): 32 - 33
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    Batcher and banyan chips that are suitable for broadband packet switch applications, simultaneously accommodate 32-bit serial packet channels, and are building blocks for larger networks are discussed. 1.2- mu m CMOS Batcher and banyan chips were tested at bit rates of 170 Mb/s. The chips require a single 5-V supply, dissipate approximately 1.5 W, provide 5.44-Gb/s switching capacity, and are packaged in 84-pin leadless ceramic chip carriers (LCC) for conventional testing. An N-input by an N-output (N*N) Batcher or banyan network is a rectangular array of identical 2*2 processing elements (cells). A processing element can take on one of two states. Each network accomplishes distributed processing over serial bit streams. The bit streams are network binary output addresses presented most significant bit first. The algorithm executed by a given network depends on the state determination logic of the 2*2 elements, as well as on the wiring permutations between successive columns in the array. Batcher networks sort packets according to output address, whereas banyan networks deliver packets to their desired output address.<> View full abstract»

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  • A 270 kbit/s 35 mW modulator IC for GSM cellular radio hand-held terminals

    Page(s): 34 - 35
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    The modulator IC has been designed to integrate all analog baseband processing components of the European Groupe Special Mobile (GSM) digital cellular radio terminals onto a single component. The IC is located at the interface of the analog 900-MHz radio-frequency part and the baseband digital signal processing part of the mobile terminal. The modulator part time-multiplexes the receive and transmit operations and combines low-noise receive circuitry with a digital modulator. The device uses digital waveform generation and a balanced quadrature representation for both modulation and demodulation of the Gaussian minimum-shift-keying (GMSK) signal. To enhance testability of the high-density printed-circuit boards, advanced test features have also been implemented in the modulator IC. In the transmit direction, the modulator IC converts digitally encoded speech or data at an instantaneous rate of 270 kb/s to the I (in-phase) and Q (quadrature) analog signals which are used to modulate a 900-MHz carrier.<> View full abstract»

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  • A 5 V front end chip for a universal voiceband modem

    Page(s): 36 - 37
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    A monolithic circuit designed for a 5-V, 1.2- mu m CMOS process combining a full analog front end with all of the logic functions that, along with one or two external digital signal processor (DSP) chips, can implement all of the voice-band modem standards from 300 to 14400 b/s is described. The analog portion of the circuit occupies 23 kmil/sup 2/ (14.9 mm/sup 2/). Combined with roughly 6000 gates of random logic, I/O pads, and supply buses, the die area totals 63 kmil/sup 2/ (40.7 mm/sup 2/). By being designed for operation with a single 5-V supply, analog circuits may use current high-density processes and migrate to future denser processes. Although analog circuitry will not scale as fast as digital circuitry, performance levels can be maintained. This circuit illustrates the potential for combining high-performance analog functions with complex digital functions on a single VLSI chip, using high-density processes.<> View full abstract»

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  • A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store

    Page(s): 42 - 43
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    A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using a data-flow clocking scheme. A floating-point unit performs single- and double-precision floating-point operations concurrently with an integer unit. The chip is fabricated using 0.8- mu m double-metal CMOS technology. About 1M transistors are contained in the 14.85*15. 13-mm die housed in a 238-pin pin-grid array (PGA).<> View full abstract»

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  • A 500 MHz microprocessor with a very long instruction word architecture

    Page(s): 44 - 45
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    A 32-b very-long-instruction-word (VLIW) chip fabricated in a double-metal 1.5- mu m CMOS process using e-beam direct-write-on-wafer lithography is discussed. The chip contains 77 K transistors on 78 mm/sup 2/. It is dedicated to running scalar integer applications. The chip consists of several independent functional units controlled on a cycle-by-cycle basis by a 200-b instruction. All units are pipelined and all stages operate in lock step, controlled by a single global clock. All units are connected to a shared on-chip multiport memory from which they take operands and into which they write results. Any previously computed result can be used as any operand of any unit. Ideally, six native operations can be initiated every cycle. In practice, the utilization of units will depend on the fine-grain parallelism that the application provides. Each unit (except the constant unit) gets an extra Boolean operand from the multiport guard memory. The guard controls whether the operation scheduled on the unit completes and whether the operation has any side effect on the processor state, such as completing a store or raising an arithmetic exception. All guards are independent and are used efficiently by the compiler to reduce the branch delay penalty drastically. A special design is required to get the necessary bandwidth from the multiport memory.<> View full abstract»

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  • An 18 ns 56-bit multiply-adder circuit

    Page(s): 46 - 47
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    A multiply-adder that achieves a 56-b X*X+Z function with cycle time of 18 ns in a 1- mu m CMOS technology is discussed. The organization requires only two pipeline stages, ensuring quick recovery from branch instructions. The design is for the fraction part of a 64-b multiply-adder and is itself 56 b wide at input and output. To achieve high performance and reasonable density, it uses Booth encoding and a Wallace tree array. Data are captured at the input latches and routed immediately to the Booth encoders, which, in addition to encoding the X input, also provide driven Y and Y-bar signals for the array. The Z input is also captured and routed to the Z shifter. Encoded X, Y-bar, and Z and shifted Z signals are all routed to the partial product array. Booth encoding for 56 b produces 29 partial products; the Z input raises the number of terms to be added to 30. The partial product array reduces this to three, at which point a second latch captures the reduced result. After the latch, the three terms are reduced to two in a full adder, and the resulting two terms added and renormalized.<> View full abstract»

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  • System, process, and design implications of a reduced supply voltage microprocessor

    Page(s): 48 - 49
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    The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% faster than the previous generation and comprises a processor chip, a floating-point chip, a cache controller chip, and a clock chip. It operates at 62.5 MHz under worst-case conditions. Micrographs of each design are given. Power and packaging specifications for each chip and the 3.3-V, 1.0- mu m (drawn) process specifications are tabulated. A high-temperature schmoo plot for the CPU chip is also given.<> View full abstract»

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  • A mainframe processor in CMOS technology with 0.5 mu m channel length

    Page(s): 50 - 51
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    A prototype of a processor chip set with a mainframe architecture is implemented using five CMOS standard cell chips. High performance is achieved by wide buses and a RISC- (reduced-instruction-set-computer) like implementation of frequently used instructions. The chip set consists of four units: (1) an instruction processor chip which fetches and decodes the instructions and contains the microcode storage; (2) cache chips which contain the address translation for up to 19 virtual address spaces, a four-way set-associative 16-kByte data/instruction cache, and a 32-B instruction buffer, which is loaded 16 B/cycle from the cache; (3) a fixed-point processor chip which contains the fixed-point registers and arithmetic and a second adder for the address calculation (base+displacement+index); (4) a floating-point processor chip which contains the floating-point registers, multiplier, and arithmetic unit. The processor is based on a four-stage pipeline (five stages for floating-point instructions).<> View full abstract»

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  • A 90 MHz CMOS RISC CPU designed for sustained performance

    Page(s): 52 - 53
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    A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<> View full abstract»

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  • An 85 ns 16 Mb CMOS EPROM with alterable word organization

    Page(s): 56 - 57
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    An 85-ns, 16-Mb CMOS EPROM which features alterable word organization and can be configured as either 1 M*16 b or 2 M*8 b by controlling an input signal is described. The redundancy circuit consists of an erasable PROM cell and an unerasable PROM cell for the storage of a nonfunctional address. Divided bit lines and tungsten polycide word lines are the keys to 85-ns access time. This device meets the requirements for high-density EPROMs to be used with 16-b or 32-b microprocessors. The EPROM uses 0.6- mu m n-well CMOS technology. The 2.0*1.8- mu m core cell has been scaled using (1) self-aligned trench isolation refilled with BPSG, (2) oxide-nitride-oxide (ONO) interpoly dielectrics, and (3) a bit-line contact with a silicide pad and selective chemical-vapor-deposition (CVD) tungsten. The resulting 16-Mb EPROM has a die area of 7.1*17.1 mm. Trench isolation technology minimizes the spacing between memory cells and ensures durability against the high gate voltage used in programming. Two ONO structures with a thickness equivalent to 20 nm of oxide serve as the interpoly dielectrics. To reduce the parasitic resistance of the core cell transistor, a 200-nm-thick tungsten silicide layer and a selectively deposited tungsten plug are used for the bit-line contact.<> View full abstract»

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  • A 16 ns 1 Mb CMOS EPROM

    Page(s): 58 - 59
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    A 64 K*16-b CMOS EPROM which achieves 16-ns access time using differential sensing with a constant-bias circuit is described. A compact test sense amplifier circuit in parallel with the main sense amplifier guarantees sufficient threshold voltage shift for the programmed cell for high-speed sensing. Complementary data are programmed into the pair of FAMOS transistors, which form one memory cell. The device is fabricated with double-layer-metal, 0.8- mu m n-well CMOS technology.<> View full abstract»

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  • An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

    Page(s): 60 - 61
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    An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme.<> View full abstract»

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  • A 55 ns 4 Mb EPROM with 1-second programming time

    Page(s): 62 - 63
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    A 55-ns, 4-Mb (256-kW*16 b) EPROM with a 1-s programming time is described. By use of 0.8- mu m lithography, a memory cell size of 2.8*2.8 mu m/sup 2/ is achieved, resulting in an 8.13*9.27 mm-die. A polycide structure is used to decrease the word line resistance and interconnection resistance, and a lightly doped drain (LDD) structure is used in the peripheral gates of pMOS and nMOS transistors to prevent degradation of characteristics induced by hot carriers. A double-well structure is adopted to improve the characteristics of short-channel pMOS transistors by optimizing the concentration of well regions. The process parameters for this device are summarized. To decrease the word line resistance, the memory array is divided into four planes, with one X-decoder for each pair of planes. This results in a 25% improvement in the access time, with a 10% die size penalty.<> View full abstract»

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  • A 35 ns 256 K CMOS EEPROM with error correcting circuitry

    Page(s): 64 - 65
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    A 35-ns-access-time 256 K (32*8) EEPROM using a double-poly/double-metal n-well 1.0- mu m CMOS process, a standard two-transistor EEPROM cell, pseudodifferential sensing, and address transition detection (ATD) is described. Pseudodifferential sensing using a reference cell is used rather than the more area-intensive fully differential cell approach. In order to achieve endurance and data retention requirements at minimal die size penalty, modified Hamming codes error correcting circuitry (ECC) was implemented instead of the O-cell approach. The improvement in data retention is about two orders of magnitude over a noncorrected version. The CMOS process provides for separate optimization of high-speed read-path, as well as high-voltage write-path, devices. The high-speed devices are approximately 1.0- mu m-effective-channel-length, 23-nm gate-oxide lightly doped drain (LDD) devices, whereas the high-voltage devices are implemented in a (densely doped drain) DDD structure with about 40-nm gate-oxide thickness.<> View full abstract»

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  • A 4 ns BiCMOS translation-lookaside buffer

    Page(s): 66 - 67
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    A 64-entry, fully associative translation lookaside buffer (TLB) which has pin-to-pin address translation time of 3.6 ns is described. This translation speed is achieved with a BiCMOS content addressable memory (CAM) and static-random-access-memory (SRAM) arrays that maintain small signal swings throughout the critical translation path.. The TLB has been integrated as a stand-alone chip in a 0.8- mu m BiCMOS technology. The circuit operates from a 5.2-V supply with emitter-coupled-logic (ECL) compatible input and output levels. The power dissipation, excluding the power dissipated in the physical address output buffers, is less than 600 mW.<> View full abstract»

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  • A 3.5 ns, 1 Watt, ECL register file

    Page(s): 68 - 69
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    A 36-b (32-b words with byte parity) by 32-word triple-ported register file designed to be used as a macrocell in an emitter-coupled-logic (ECL) reduced-instruction-set-computer (RISC) microprocessor is discussed. The goal was to produce a dense, low-power design, since the floating-point coprocessor requires two register files. The chips are fabricated using a 2- mu m, triple-implanted, three-level metal bipolar process. This process yields small, low-capacitance transistors, ideal for running at low currents. The minimum-size transistor has a collector series resistance of 1500 Omega , so transistor sizing is very important in this technology. A standard ECL inverter running at an 80- mu A tail has a nominal delay of 350 ps. The metal pitches are 4 mu m on metal 1 and metal 2 and 8 mu m on metal 3.<> View full abstract»

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  • A single-chip, functional tester for VLSI circuits

    Page(s): 84 - 85
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    A single-chip functional tester for VLSI circuits that integrates the vector memory, the error memory, a decompressor, and 16 sets of independently controlled pin electronics on a 9.0*9.4-mm chip is described. The device contains over 200 K transistors and is fabricated using a 1.6- mu m CMOS technology. The integrated pin electronics support a per-pin tester architecture, allowing the transitions for each pin to be independently adjusted to better than 1 ns. The chip dissipates less than 0.75 W running at 25 M vectors/s. By integrating all tester functions on a single chip, it is possible to build all extremely compact tester. A 256-pin tester requires only 16 chips. This size makes it possible to reduce the length of the transmission line between the device under test and the tester to under 10 cm, minimizing signal reflections and enabling the delivery of high-fidelity waveforms.<> View full abstract»

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