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# IEEE Transactions on Computers

## Issue 99

Early Access articles are new content made available in advance of the final electronic or print versions and result from IEEE's Preprint or Rapid Post processes. Preprint articles are peer-reviewed but not fully edited. Rapid Post articles are peer-reviewed and edited but not paginated. Both these types of Early Access articles are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 59
• ### Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks

Publication Year: 2017, Page(s): 1
| | PDF (610 KB) |  Media

Mixed-criticality models are an emerging paradigm for the design of real-time systems because of their significantly improved resource efficiency. However, formal mixed-criticality models have traditionally been characterized by two impractical assumptions: once any high-criticality task overruns, all low-criticality tasks are suspended and all other high-criticality tasks are assumed to exhibit h... View full abstract»

• ### Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy

Publication Year: 2017, Page(s): 1
| | PDF (1510 KB)

Embedded systems in several domains such as avionics and automotive are subject to inspection from certification authorities. These authorities are interested in verifying the safety-critical aspects of a system and, typically, do not certify non-critical parts. The design of such Mixed-Criticality Systems (MCS) has received increasing attention in recent years. However, systems susceptibility to ... View full abstract»

• ### Digit Serial Methods with Applications to Division and Square Root

Publication Year: 2017, Page(s): 1
| | PDF (634 KB)

We present a generic digit serial method (DSM) to compute the digits of a real number V. Bounds on these digits, and on the errors in the associated estimates of V formed from these digits, are derived. To illustrate our results, we derive bounds for a parameterized family of high-radix algorithms for division and square root. These bounds enable hardware designers to determine, for example, wheth... View full abstract»

• ### MC-Fluid: Multi-core Fluid-based Mixed-Criticality Scheduling

Publication Year: 2017, Page(s): 1
| | PDF (1627 KB)

Owing to growing complexity and scale, safetycritical real-time systems are generally designed using the concept of mixed-criticality, wherein applications with different criticality or importance levels are hosted on the same hardware platform. To guarantee non-interference between these applications, the hardware resources, in particular the processor, are statically partitioned among them. To o... View full abstract»

• ### ADAS on COTS with OpenCL: A Case Study with Lane Detection

Publication Year: 2017, Page(s): 1
| | PDF (211 KB)

The concept of autonomous cars is driving a boost for car electronics and the size of automotive electronics market is foreseen to double by 2025. How to benefit from this boost is an interesting question. This article presents a case study to test the feasibility of using OpenCL as the programming language and COTS components as the underlying computing platforms for ADAS development. For represe... View full abstract»

• ### Lightweight Ciphers and their Side-channel Resilience

Publication Year: 2017, Page(s): 1
| | PDF (5261 KB)

Side-channel attacks represent a powerful category of attacks against cryptographic devices. Still, side-channel analysis for lightweight ciphers is much less investigated than for instance for AES. Although intuition may lead to the conclusion that lightweight ciphers are weaker in terms of side-channel resistance, that remains to be confirmed and quantified. In this paper, we consider various si... View full abstract»

• ### Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory

Publication Year: 2017, Page(s): 1
| | PDF (7419 KB)

Index structures can significantly accelerate the data retrieval operations in data intensive systems, such as databases. Tree structures, such as B+-tree alike, are commonly employed as index structures; however, we found that the tree structure may not be appropriate for Non-Volatile Memory (NVM) in terms of the requirements for high-performance and high-endurance. This paper studies what is the... View full abstract»

• ### Designing Checksums for Detecting Errors in Fast Unitary Transforms

Publication Year: 2017, Page(s): 1
| | PDF (307 KB)

Parity computations, checksums, over the input and output data of fast unitary transforms are compared, down to roundoff noise levels, to detect the effects from a single error on any one line between stages of the fast algorithm. Error spaces and their dual spaces guide the design process. View full abstract»

• ### Randomized Mixed-Radix Scalar Multiplication

Publication Year: 2017, Page(s): 1
| | PDF (1798 KB)

A set of congruence relations is a $\mathbb{Z}$-covering if each integer belongs to at least one congruence class from that set. In this paper, we first show that most existing scalar multiplication algorithms can be formulated in terms of covering systems of congruences. Then, using a special form of covering systems called exact n-covers, we present a novel uniforml... View full abstract»

• ### Efficient Software Implementation of Ring-LWE Encryption on IoT Processors

Publication Year: 2017, Page(s): 1
| | PDF (380 KB)

Embedded processors have been widely used for building up Internet of Things (IoT) platforms, in which the security issue is becoming critical. This paper studies efficient techniques of lattice-based cryptography on these processors and presents the first implementation of ring-LWE encryption on ARM NEON and MSP430 architectures. For ARM NEON architecture, we propose a vectorized version of Itera... View full abstract»

• ### Achieving Load Balance for Parallel Data Access on Distributed File Systems

Publication Year: 2017, Page(s): 1
| | PDF (2640 KB)

The distributed file system, HDFS, is widely deployed as the bedrock for many parallel big data analysis. However, when running multiple parallel applications over the shared file system, the data requests from different processes/executors will unfortunately be served in a surprisingly imbalanced fashion on the distributed storage servers. These imbalanced access patterns among storage nodes are ... View full abstract»

• ### A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security

Publication Year: 2017, Page(s): 1
| | PDF (2946 KB)

Arbiter Physically Unclonable Functions (APUFs), while being relatively lightweight, are extremely vulnerable to modeling attacks. Hence, various compositions of APUFs such as XOR APUF and Lightweight Secure PUF have been proposed to be secure alternatives. Previous research has demonstrated that PUF compositions have two major challenges to overcome: vulnerability against modeling and statistical... View full abstract»

• ### ClusterFetch: A Lightweight Prefetcher for Intensive Disk Reads

Publication Year: 2017, Page(s): 1
| | PDF (470 KB)

By overlapping disk accesses with computation-intensive operations, prefetching can reduce delays in launching an application and in loading significant amounts of data while the application is running. The key to effective prefetching is making the tradeoff between the mining accuracy of selecting relevant blocks, and the time to decide those blocks. To address this problem, we propose a new pref... View full abstract»

• ### Principal Component Analysis based Filtering for Scalable, High Precision k-NN Search

Publication Year: 2017, Page(s): 1
| | PDF (9954 KB)

Approximate k Nearest Neighbours (AkNN) search is widely used in domains such as computer vision and machine learning. However, AkNN search in high dimensional datasets does not scale well on multicore platforms, due to its large memory footprint. Parallel AkNN search using space subdivision for filtering helps reduce the memory footprint, but its loss of precision is unstable. In this paper, we p... View full abstract»

• ### Techniques to reduce switching and leakage energy in unrolled block ciphers

Publication Year: 2017, Page(s): 1
| | PDF (1148 KB)

Energy consumption of block ciphers is critical in resource constrained devices. Unrolling has been explored in literature as a technique to increase efficiency by eliminating energy spent in loop control elements such as registers and multiplexers. However these savings are minimal and are offset by the increase in glitching power that comes with unrolling. We propose an efficient latch-based gli... View full abstract»

• ### $D^{3}$: A Dynamic Dual-phase Deduplication Framework for Distributed Primary Storage

Publication Year: 2017, Page(s): 1
| | PDF (2412 KB)

Deploying deduplication for distributed primary storage is a sophisticated and challenging task, considering that the demands of low read/write latency, stable read/write performance, and efficient space saving are all of paramount importance. Unfortunately, existing schemes cannot present a satisfactory solution for the aforementioned requirements simultaneously. In this article, we propose View full abstract»

• ### Bi-Objective Optimization of Data-Parallel Applications on Homogeneous Multicore Clusters for Performance and Energy

Publication Year: 2017, Page(s): 1
| | PDF (1559 KB) |  Media

Performance and energy are now the most dominant objectives for optimization on modern parallel platforms composed of multicore CPU nodes. The existing intra-node and inter-node optimization methods employ a large set of decision variables but do not consider problem size as a decision variable and assume a linear relationship between performance and problem size and between energy consumption and... View full abstract»

• ### Compact CA-based Single Byte Error Correcting Codec

Publication Year: 2017, Page(s): 1
| | PDF (400 KB)

Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are generally used in memory systems. But in case of multipl... View full abstract»

• ### Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs

Publication Year: 2017, Page(s): 1
| | PDF (1182 KB)

Soft-processors implemented on SRAM-based FPGAs are increasingly being adopted in on-board computing for space and avionics applications due to their flexibility and ease of integration. However, efficient component-level protection techniques for these processors against radiation-induced upsets are necessary otherwise as system failures could manifest. A register file is one of the critical stru... View full abstract»

• ### Genetic Programming for Energy-efficient and Energy-scalable Approximate Feature Computation in Embedded Inference Systems

Publication Year: 2017, Page(s): 1
| | PDF (3436 KB)

With the increasing interest in deploying embedded sensors in a range of applications, there is also interest in deploying embedded inference capabilities. Doing so under the strict and often variable energy constraints of the embedded platforms requires algorithmic, in addition to circuit and architectural, approaches to reducing energy. A broad approach that has recently received considerable at... View full abstract»

• ### Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems

Publication Year: 2017, Page(s): 1
| | PDF (3688 KB)

All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores, referred to as bubbles, can be placed near active cores for heat dissipation so that the active cores can run at a higher frequency level, boosting the performance of active cores and applications. Budgeting i... View full abstract»

• ### DuCNoC: A High-Throughput FPGA-based NoC simulator using Dual-Clock Lightweight Router Micro-Architecture

Publication Year: 2017, Page(s): 1
| | PDF (1783 KB)

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary,... View full abstract»

• ### Approximate DCT Image Compression using Inexact Computing

Publication Year: 2017, Page(s): 1
| | PDF (951 KB) |  Media

This paper proposes a new framework for digital image processing; it relies on inexact computing to address some of the challenges associated with the discrete cosine transform (DCT) compression. The proposed framework has three levels of processing; the first level uses approximate DCT for image compressing to eliminate all computational intensive floating-point multiplications and executing the ... View full abstract»

• ### On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks

Publication Year: 2017, Page(s): 1
| | PDF (5320 KB)

Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded monitoring instruments detect faults to the time when the fault manager localizes the faults. In this article, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected faults are automatically included in the scan path, and a fault detection and lo... View full abstract»

• ### Start Simple and then Refine: Bias-Variance Decomposition as a Diagnosis Tool for Leakage Profiling

Publication Year: 2017, Page(s): 1
| | PDF (2349 KB)

Evaluating the resistance of cryptosystems to side-channel attacks is an important research challenge. Profiled attacks reveal the degree of resilience of a cryptographic device when an adversary examines its physical characteristics. So far, evaluation laboratories launch several physical attacks (based on engineering intuitions) in order to find one strategy that eventually extracts secret infor... View full abstract»

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org