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1994 Second International Conference on Advanced A-D and D-A Conversion Techniques and their Applications

6-8 Jul 1994

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Displaying Results 1 - 25 of 32
  • An 8-bit 3MS/s CMOS two-step flash converter for low voltage mixed signal CMOS integration

    Publication Year: 1994, Page(s):71 - 75
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (204 KB)

    Many large, mainly digital system ICs require on-chip A/D conversion for their input interface, and the task of incorporating this function into a hostile environment is not trivial. As power supplies for these digital systems are reduced, the analogue functions must follow suit. In this paper we describe a two-step flash converter capable of operating at 3MS/s with a supply voltage of just 3V. Th... View full abstract»

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  • The requirements of analogue to digital converters in nuclear and X-ray spectrometry

    Publication Year: 1994, Page(s):7 - 10
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (228 KB)

    Most nuclear radiation detectors produce an output whose amplitude is proportional to the incident particle energy. The techniques of converting this amplitude into energy bins has a history spreading over 50 years. The requirements placed on ADCs for spectrometry are somewhat different than those in most other applications. The differential nonlinearity (DNL) which in most commercial ADCs is betw... View full abstract»

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  • Self-calibration in high speed current steering CMOS D/A converters

    Publication Year: 1994, Page(s):148 - 152
    Cited by:  Papers (2)  |  Patents (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (252 KB)

    This paper describes a novel approach to self-calibration applied to current steering CMOS DACs. The basic idea is to use regulated cascode current sources with degenerated resistances. The drop voltage across the degenerated resistance measures the current, thereby allowing calibration. A suitable architecture for achieving continuous calibration is described. The paper also discusses some design... View full abstract»

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  • Design of CMOS A/D converters with folding and/or interpolating techniques

    Publication Year: 1994, Page(s):76 - 81
    Cited by:  Papers (4)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (296 KB)

    For resolutions around 8 bit the flash A/D converter is the fastest possible architecture. The sampling speed of the flash converter is limited to the maximum speed of a comparator in that technology. All other A/D converter architectures, such as two step, pipelined, etc., have a comparator as a building block, so the sampling speed of these converters is maximum that of the flash converter based... View full abstract»

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  • The design of a sigma-delta codec for mobile telephone applications

    Publication Year: 1994, Page(s):11 - 17
    Cited by:  Papers (5)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (416 KB)

    The algorithmic, structural, and architectural design of a 13-bit linear sigma-delta ADC and DAC for use with digital mobile telephone systems is described. Analog and digital third-order single-loop modulators running at 512 kHz (64X oversampled) are used to keep the power dissipation low. The ADC uses a two-stage decimation process. The first stage uses a fourth-order “slink” filter ... View full abstract»

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  • The use of multi tone dither in high speed A/D conversion

    Publication Year: 1994, Page(s):153 - 158
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (248 KB)

    The use of `dither' to extend the dynamic range of an analogue to digital converter is well known in digital audio. Dither signals are usually either noise or a sinewave. Noise performs a better dithering action than a sinewave, but cannot be removed by filtering. This paper describes the use of a three tone dither signal that has an improved dithering action and can be removed by filtering. Resul... View full abstract»

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  • A high precision ADC system for instrumentation

    Publication Year: 1994, Page(s):60 - 64
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (260 KB)

    Pulse Density Modulation and especially Sigma Delta techniques are employed preferably for a wide range of applications. No trimming is required and no complicated calibration circuitry has to be implemented. This type of converters provide low cost and reasonably small silicon area is utilized. Although there are limitations in multiplexing and control loop applications, Pulse Density Modulation ... View full abstract»

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  • Linearization of class D output stages for high-performance audio power amplifiers

    Publication Year: 1994, Page(s):136 - 141
    Cited by:  Papers (7)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (344 KB)

    A system is described which uses a quantized feedback technique to reduce the distortion generated by a class D PWM amplifier, thus making it more suitable for use in a high-performance audio system. The technique is applicable to digital PWM and applies local error correction in a noise shaping loop to reduce output-stage distortion and thus achieve a performance closer to that defined by the dig... View full abstract»

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  • A two-step flash ADC for digital CMOS technology

    Publication Year: 1994, Page(s):48 - 51
    Cited by:  Papers (4)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (264 KB)

    This paper describes a current-mode two-step flash ADC suitable for integration on digital CMOS technology. The converter architecture comprises a low resolution flash employing high-speed current comparators, a thermometer-weighted current-mode DAC and a simple current subtractor and amplifier for generating the residue current. For a resolution of 7 bits and conversion frequency up to 50 MHz thi... View full abstract»

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  • A 16X oversampling CMOS ADC with 100 kHz bandwidth and 90dB SNR

    Publication Year: 1994, Page(s):82 - 89
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    Oversampled sigma-delta ADCs have considerable advantages for high-resolution applications compared to other ADC architectures, including relaxed requirements for component matching, amplifier and comparator performance, and improved noise immunity. These advantages have led to their widespread adoption for applications such as instrumentation, seismology and digital audio, with signal bandwidths ... View full abstract»

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  • The phase performance of digital radio frequency memories (DRFMs)

    Publication Year: 1994, Page(s):18 - 23
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (336 KB)

    The Digital Radio Frequency Memory (DRFM) is a device which samples a radio signal, usually at microwave frequencies, and regenerates it after a controlled delay. It is anticipated that DRFMs will replace analogue delay lines in the next generation of Radar Test and Electronic Counter Measures (ECM) equipment. The minimum DRFM consists of: a downconverter from radio frequencies to baseband, a digi... View full abstract»

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  • Automatic design of ΣΔ modulators from specifications to silicon

    Publication Year: 1994, Page(s):96 - 101
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (340 KB)

    We present a tool developed as part of the ESPRIT-AD2000 Project which, starting from high-level specifications of SC ΣΔ modulators, calculates optimum specifications for their building blocks and then, optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design, and innovative heuristics for increased co... View full abstract»

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  • A high fidelity decimation filter for sigma-delta converters

    Publication Year: 1994, Page(s):30 - 35
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (380 KB)

    This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order ΣΔ modulator running at 4096 kHz. This paper also reports on the fixe... View full abstract»

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  • A DNL measurement on an oversampling noise shaping ADC

    Publication Year: 1994, Page(s):181 - 185
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (204 KB)

    Oversampling Noise Shaping ADCs (ONSAs) are recognised as being capable of very good low signal performance, because they do not exhibit the Differential Non Linearity (DNL) and variations in Differential Gain that other ADC architectures exhibit. DNL generally causes subsequent signal processing to break down as the signal gets smaller, and is a very common cause of problems with ADCs. Although O... View full abstract»

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  • Precision behavioural modelling of circuit components for data converters

    Publication Year: 1994, Page(s):110 - 115
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (352 KB)

    This paper describes the use of behavioural modelling for accurate and efficient simulation of data converters. Examples of behavioural models of building blocks for different classes of converters are provided and analysed. The need for dedicated high-level simulation tools for particular system architectures is also discussed. Simulation results show the effectiveness of the proposed methods in ... View full abstract»

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  • Error feedback loops linearize direct digital synthesizers

    Publication Year: 1994, Page(s):159 - 162
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (196 KB)

    The fidelity of a signal formed by the sequence of recalling stored digital samples from a look-up table and then converting these sample amplitudes to a waveform in a digital-to-analog converter (DAC) is affected by the time and amplitude quantization of the process. The size of the look-up table, hence the number of bits in the addressing scheme, affects the signal's time resolution and results ... View full abstract»

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  • Design considerations for current domain regenerative comparators

    Publication Year: 1994, Page(s):65 - 70
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (348 KB)

    In voltage domain applications, regenerative comparators are a common choice where high speed operation is required. Their basic structure is simple, consisting of pairs of cross coupled devices in a positive feedback or regenerative configuration. However, such structures are notoriously sensitive to offsets and hence when precise operation is required they usually form the second (or later) stag... View full abstract»

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  • Cascading bandpass sigma-delta A-D converters

    Publication Year: 1994, Page(s):1 - 6
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (208 KB)

    This paper describes an extension of the technique of cascading of two bandpass sigma-delta converters to provide a higher dynamic range converter. As these converters operate in the continuous time mode, matching of the two feedforward signal paths must be controlled to a high degree of accuracy in both phase and amplitude. In general this is beyond the stability of the analogue circuits involved... View full abstract»

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  • Self-calibration for high-speed, high-resolution D/A converters

    Publication Year: 1994, Page(s):142 - 147
    Cited by:  Papers (5)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (308 KB)

    This paper proposes the use of digitally-controlled trimmable current sources and self-calibration to obtain a high-speed, high-resolution CMOS D/A converter. An accuracy of 14-bits has been targeted, and simulation results have shown a 15ns settling time to 0.5LSB. A full-scale output current of 10-20 mA allows 50Ω loads to be driven directly. The DAC can be fabricated using a standard digi... View full abstract»

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  • A 500 kHz 14-bit BiCMOS ADC

    Publication Year: 1994, Page(s):52 - 59
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper presents the design of a flexible 500 kHz 14-bit ADC for manufacture with 2μm BiCMOS technology and optimised for use in multiplexed applications. The paper begins by outlining the ADC application and goes on to provide an account of the algorithm, architecture and block-level implementation. The design is based on the classic two-pass residue algorithm, but uses digital signal proce... View full abstract»

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  • Improved state-space and phase-plane error table compensation of analogue-to-digital converters using pseudo-random calibration signals

    Publication Year: 1994, Page(s):130 - 135
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    This paper shows that the use of pseudo-random calibration signals gives much better error table coverage than the conventional sinusoidal signals, resulting in better ADC compensation. The phase-plane and state-space error table coverage of the new random calibration signals is compared to that of the conventional sinusoidal calibration signals. For a known nonlinear system, the state-space error... View full abstract»

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  • A dual 3.4V bitstream continuous calibration CMOS D/A converter with 110 dB dynamic range

    Publication Year: 1994, Page(s):42 - 47
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (420 KB)

    A new generation D/A converter is presented, combining a true 18-bit dynamic range with easy application. This is achieved by introducing oversampling to 96 fs, digital filtering and noise-shaping. The actual digital-to-analogue conversion is done by a continuously calibrated current D/A converter on the same die. System and circuit design are both optimised to avoid degradation of the ... View full abstract»

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  • Low power 13 bit ADCs for ASIC applications

    Publication Year: 1994, Page(s):90 - 95
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (368 KB)

    A family of analogue to digital converters are described for system integration ASIC applications. The converter architecture gives a current consumption of 10 mW coupled with an analogue core size of 2 mm 2. The individual converters maintain 13 bit dynamic range and linearity with a sampling rate of 40 kHz. Area and power consumption of the circuit are optimised for ASIC applications,... View full abstract»

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  • Quantiser requirements for next-generation uncooled thermal imagers

    Publication Year: 1994, Page(s):24 - 29
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (360 KB)

    Detector technologies are being developed which offer the potential for thermal imagers to become much more widespread, making use of ferroelectric FPAs to reduce cost and improve the ease with which thermal imagers can be used, both in civil and military applications. The critical electronic components, apart from the detector array itself, are the quantiser components. The signal conditioning ar... View full abstract»

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  • Measurement of nonlinearity in high-resolution sigma-delta converters

    Publication Year: 1994, Page(s):175 - 180
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (364 KB)

    Sigma-delta conversion techniques are now common in high-resolution analog-to-digital (AD) and digital-to-analog (DA) converter design, and are capable of achieving high dynamic range with low distortion. One of the biggest problems in evaluating the performance of such converters is in measuring nonlinear errors at either the design stage (by simulation) or in physical realisations. This paper re... View full abstract»

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