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2006 Workshop on High Performance Switching and Routing

7-9 June 2006

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  • 2006 Workshop on High Performance Switching and Routing (IEEE Cat. No. 06EX1229C)

    Publication Year: 2006
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  • 2006 Workshop on High Performance Switching and Routing - Copyright

    Publication Year: 2006, Page(s): ii
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  • HPSR 2006 executive Committee

    Publication Year: 2006, Page(s): v
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  • HPSR 2006 technical Program Committee

    Publication Year: 2006, Page(s):vi - vii
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  • Additional reviewers of HPSR 2006

    Publication Year: 2006, Page(s):viii - x
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  • Table of contents

    Publication Year: 2006, Page(s):xi - xvi
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  • Technical section 1 A - Router and switch architectures I

    Publication Year: 2006, Page(s): 2
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  • Forwarding model of backplane Ethernet for open architecture router

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (178 KB) | HTML iconHTML

    Diversified IP services have recently required flexible and scalable edge routers to support advanced service functions such as IPsec VPN and application layer firewalls. However, those functions cannot be integrated into existing routers easily, and this prevents required routers from becoming available. A common forwarding model of backplane Ethernet for a router supporting separate control, lin... View full abstract»

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  • RFC 2544 performance evaluation and internal measurements for a Linux based open router

    Publication Year: 2006
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    Recent technological advances give a good chance to do something really effective in the field of open Internet equipments, also called open routers (ORs). Some initiatives have been activated since the last few years to investigate the OR and related issues. But despite these activities, large interesting areas still require a deeper investigation. This work tries to give a contribution by report... View full abstract»

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  • Resource virtualisation of network routers

    Publication Year: 2006
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB) | HTML iconHTML

    There is now considerable interest in applications that transport time-sensitive data across the best-effort Internet. We present a novel network router architecture, which has the potential to improve the quality of service guarantees provided to such flows. This router architecture makes use of virtual machine techniques, to assign an individual virtual routelet to each network flow requiring Qo... View full abstract»

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  • Retransmission in slotted optical networks

    Publication Year: 2006
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (159 KB) | HTML iconHTML

    We consider an all-optical slotted network with contention-based operation where optical switches have neither an electronic buffer nor an optical buffer inside them. Since retransmission could be the cheapest contention resolution scheme in this network, we study and compare both the conventional and prioritized retransmission schemes. In the former technique, traffic retransmission continues unt... View full abstract»

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  • Technical section 1 b - Network processors, IP table lookup and packet classification

    Publication Year: 2006, Page(s): 27
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  • Performance evaluation and cache behavior of LC-trie for IP-address lookup

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    Many IP-address lookup software algorithms use a trie-like data structure to perform longest prefix match. LC-trie is an efficient algorithm that uses level compression and path compression on tries. By using realistic and synthetically generated traces, we study the performance of the LC-trie algorithm. Our study includes trie search depth, prefix vector access behavior, cache behavior, and packe... View full abstract»

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  • Divide-and-conquer: a scheme for IPv6 address longest prefix matching

    Publication Year: 2006
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Longest prefix matching (LPM) is a challenging subject because of the increasing routing table size, the increasing link speed, and the increasing Internet traffic with decreasing packet size. With the advent of IPv6, it requires reconsideration of the previous schemes particularly designed for IPv4. We introduce the first algorithm that we are aware of to employ divide-and-conquer method for IPv6... View full abstract»

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  • Markers-based space decomposition algorithm: a new algorithm for multi-fields packet classification

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (105 KB) | HTML iconHTML

    Packet classification is a central function in several network applications such as firewalls and QoS-enhanced routers. Several schemes were proposed for fast packet classification, but few ones support incremental updates. In this paper, we present a new multi-fields packet classification algorithm and show its advantages compared to previous proposed algorithms. We present performance measuremen... View full abstract»

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  • Evaluation of cache base network processor by using real backbone network trace

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (422 KB) | HTML iconHTML

    In this paper a novel cache-based packet-processing-engine (PPE) architecture that achieves high packet-processing throughput with low-power consumption is proposed and evaluated. As network packets of the same header information appear repeatedly in a short time, a special cache, the so called header-learning cache (HLC), memorizes the packet-processing method and enables most packets to skip the... View full abstract»

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  • Technical section 2 A - Router and switch architectures II

    Publication Year: 2006, Page(s): 55
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  • Scalable router memory architecture based on interleaved DRAM

    Publication Year: 2006
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitable for high-speed Internet routers which require both large capacity and fast access time. Some previous work has been done to combine the two technologies together and make a hybrid memory system. In this paper, we propose ano... View full abstract»

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  • Design issues for edge nodes in agile all-photonic networks

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (206 KB) | HTML iconHTML

    This paper raises the issues faced in edge node design for an agile all-photonic network (AAPN) and proposes solutions. The architecture discussed addresses several issues such as packet processing, traffic aggregation and encapsulation, buffers implementation, local scheduling, QoS provision, traffic monitoring and internal control mechanisms. The main goal of this work is to provide a detailed d... View full abstract»

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  • Architecture of an integrated router interconnected spectrally (IRIS)

    Publication Year: 2006
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    The design of optical packet routers poses significant challenges both in terms of its architecture and component design. In this paper, we evaluate several alternatives for the architecture of such routers, and describe the architecture of IRIS (integrated router interconnected spectrally), an optical router being designed at Bell Laboratories. By combining load balancing with wavelength switchin... View full abstract»

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  • Performance analysis of a practical load balanced switch

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    The load balanced (LB) switch proposed by C.S. Chang et al. (2000), (2002) consists of two stages. First, a load-balancing stage spreads arriving packets equally among all linecards. Then, a forwarding stage transfers packets from the linecards to their final output destination. The load balanced switch does not need any centralized scheduler and can achieve 100% throughput under a broad class of ... View full abstract»

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  • Technical section 2 B Switch scheduling I

    Publication Year: 2006, Page(s): 85
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  • An efficient packet scheduler for modern network processors: guarantee load balancing and packet ordering

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (451 KB) | HTML iconHTML

    Multi-processors in modern network processors (NPs) are often organized as parallel processing elements (PEs) to achieve efficient packet forwarding for 10 Gbps high-speed links. It's a challenge to schedule the incoming packets from high-speed links to be processed by multiple PEs in parallel. In this paper, we present a novel packet scheduling scheme for 10 Gbps network processors, which satisfi... View full abstract»

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  • Distributed crossbar schedulers

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    The goal of this work is to enable distributed (multi-chip) implementations of iterative matching algorithms for crossbar-based packet switches, as opposed to the traditional monolithic (single-chip) ones. The practical motivation for this effort is the design and implementation in FPGAs of a scheduler for a 64-port optical crossbar switch. Sizing experiments show that the scheduler logic must be ... View full abstract»

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  • Integrating uni- and multicast scheduling in buffered crossbar switches

    Publication Year: 2006
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    Internet traffic is a mixture of unicast and multicast flows. Integrated schedulers capable of dealing with both traffic types have been designed mainly for input queued (IQ) buffer-less crossbar switches. Combined input and crossbar queued (CICQ) switches, on the other hand, are known to have better performance than their buffer-less predecessors due to their potential in simplifying the scheduli... View full abstract»

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