International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.

5-7 Sept. 2006

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  • Authors index

    Publication Year: 2006, Page(s):445 - 447
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  • ISBN: 0-7803-9726-6 [Back cover]

    Publication Year: 2006, Page(s): 0_2
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    Publication Year: 2006, Page(s): ii
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  • Transcutaneous power and high data rate transmission for biomedical implants

    Publication Year: 2006, Page(s):374 - 378
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    The electronic implants were introduced in the human body further to a surgical operation for the neurological dysfunctions treatment as well as the help or the replacement of the organs which have difficulties. For practical and medical reasons, implants have to communicate without wire with the external world. Most of them use an inductive link to supply in power and data. In this paper, we prop... View full abstract»

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  • A high-level timing model for variability characterization of interconnect circuits

    Publication Year: 2006, Page(s):310 - 315
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    At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only during physical design but also during lo... View full abstract»

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  • Supply voltage glitches effects on CMOS circuits

    Publication Year: 2006, Page(s):257 - 261
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (465 KB) | HTML iconHTML

    Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour de... View full abstract»

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  • Dependability analysis: performance evaluation of environment configurations

    Publication Year: 2006, Page(s):335 - 340
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    Prototyping-based fault injection environments are employed to perform dependability analysis and thus predict the behavior of circuits in presence of faults. A novel environment has been recently proposed to perform several types of dependability analyses in a common optimized framework. The approach takes advantage of hardware speed and of software flexibility to achieve optimized trade-offs bet... View full abstract»

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  • Modeling of pixel sensors for image systems with VHDL-AMS

    Publication Year: 2006, Page(s):289 - 293
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    The design of mixed signal systems on chip is in a continuous growth these last few years. So the technical progress for systems integration allows the implementation of millions of active or passive pixel sensors (APS or PPS) on a same chip in order to define image matrix (system on chip). It has become crucial for the design of these systems to accurately predict their behavior prior to manufact... View full abstract»

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  • An on-line software-based self-test framework for microprocessor cores

    Publication Year: 2006, Page(s):394 - 399
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (427 KB) | HTML iconHTML

    Software-based self-test (SBST) in embedded microprocessor cores testing allows lowering test costs without loosing fault detection capabilities. Particularly in critical environments, SBST is executed during the system operating life in order to guarantee its availability and quality of service. If the test routines can be executed online but not-concurrently, then both the hardware and software ... View full abstract»

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  • A low-power oscillation based LNA BIST scheme

    Publication Year: 2006, Page(s):268 - 272
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (214 KB) | HTML iconHTML

    Test stimuli generation and power consumption are two issues that jeopardize the design of built-in self test schemes. The LNA testing approach presented herein relies on converting the amplifier into an oscillator and on using a low-power correlator to obtain a signature from the cross-correlation between the dynamic power supply current and the LNA's output voltage. In test mode a high fault cov... View full abstract»

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  • Design of secure digital communication systems using DCSK chaotic modulation

    Publication Year: 2006, Page(s):200 - 204
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Chaos-based communication can be applied advantageously only if the property of chaotic systems is suitably exploited. Chaos communication has been studied for only a little more than a decade while traditional communication schemes have been developed for nearly a century. The hope was (and still is) that for some application chaotic communication will prove to be better than traditional communic... View full abstract»

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  • An application specific NoC mapping for optimized delay

    Publication Year: 2006, Page(s):184 - 188
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    This paper presents a delay computing-model for a 2D-mesh worm hole based NoC architecture that is a widely used topology structure in NoC design. The model captures the core's message sending probability, packet length and the contention of link in the communication. The different solutions of core's mapping onto NoC architecture will cause different average delay and a genetic algorithm, which i... View full abstract»

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  • CMOS leakage power at cell level

    Publication Year: 2006, Page(s):194 - 199
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level. A characterization methodology is discussed and applied to inverter, NAND and NOR cell... View full abstract»

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  • Performance of adaptive filter used in CDMA system for multiple access interference suppressing

    Publication Year: 2006, Page(s):424 - 426
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    In a code division multiple access (CDMA) system all users share the same frequency band and they are separated from each other by (quasi)-orthogonal spreading codes. However, on dispersive broadband channels the orthogonality among codes is disrupted and multi-user access interference (MAI) is present on the received signal. Moreover, interference among symbols and chips of the same user arises. ... View full abstract»

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  • Two-pattern generation based on accumulators with 1's complement adders

    Publication Year: 2006, Page(s):365 - 369
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (269 KB) | HTML iconHTML

    Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults t... View full abstract»

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  • Accumulator - based compression in symmetric transparent RAM BIST

    Publication Year: 2006, Page(s):273 - 278
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (247 KB) | HTML iconHTML

    Symmetric transparent BIST has been proposed as a means to skip the signature prediction phase during RAM testing (required in traditional transparent BIST), therefore achieving significant reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compression is performed using single input shift registers (SISRs, for bit-organized memories) or multiple input shif... View full abstract»

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  • Design and optimisation of RF filters for multistandard RF sub-sampling receiver

    Publication Year: 2006, Page(s):105 - 109
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    This paper presents an improved sampling-based down conversion topology design with double RF filters for multi-standard RF subsampling receiver. Proposed architecture is limiting down conversion to IF domain and adding a first tunable RF filter to select multistandard RF bands. To overcome subsampling negative effects on receiver performances a second RF filter is inserted before subsampling oper... View full abstract»

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  • Implementation of a neural netwok module for fourth generation mobile equipements

    Publication Year: 2006, Page(s):431 - 436
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Pipelined recurrent neural network (PRNN) has been used with lot of success in many applications. In recent works, we have also proven that the PRNN exhibits good performances when used for interference cancellation and channel parameters estimation for the different multiple access schemes proposed as physical layer of the fourth generation (4G) networks: wideband code division multiple access (W... View full abstract»

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  • Comparison of addition structures synthesis over commercial FPGAs

    Publication Year: 2006, Page(s):413 - 417
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB) | HTML iconHTML

    This paper describes the behavior of the synthesis of several adders with different structures: lineal, like ripple carry adder, tree, like carry look ahead; array, like prefix adders; and optimized low level logic over FPGAs. The results of used resources and total delay of the resulting circuit are compared over the commercial families VIRTEX4 and STRATIX2 from Xilinx and Altera manufacturers, r... View full abstract»

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  • Hardware design and implementation of digital controller for parallel active filters

    Publication Year: 2006, Page(s):331 - 334
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (351 KB) | HTML iconHTML

    Industrial and domestic equipment actually uses a large variety of electronic circuits, which have nonlinear impedance. They provide into the network non-sinusoidal currents which outcomes include higher losses for transformer or possible overheating or over-voltage. The parallel active filtering presents one of the adequate solutions to eliminate the harmonic pollution generated by inductive load... View full abstract»

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  • Implementation of a fuzzy logic tracking path algorithm on a field programmable gate array

    Publication Year: 2006, Page(s):355 - 358
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    Since some years, most of the architectures of autonomous robots integrate the planning activity, which provides goals for the robot, with behavior-based reactivity, implemented by simple and fast control modules. The purpose of this article is the implementation of a tracking path algorithm based fuzzy logic on a field programmable gate array View full abstract»

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  • Design and implementation of an 11-bit non-linear interpolation DAC

    Publication Year: 2006, Page(s):136 - 139
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    In this paper a novel design of an 11 bit digital-to-analog converter (DAC) is introduced. The design is to be integrated in a direct digital frequency synthesizer (DDKS). The designing of a DAC is critical due to its poor performance and low speed. The proposed design consists of three modules, a linear DAC, a nonlinear DAC and a nonlinear interpolation DAC. Each module contributes in enhancing t... View full abstract»

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  • Reliability of active RF filters in nanoscale region

    Publication Year: 2006, Page(s):101 - 104
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    Hot carrier effect on active RF filter performance is studied systematically for 0.16 mum CMOS technology. Active inductor based RF filter can be used for RF and IF filters in wireless communications. Hot carrier interface state generation (HCI) and time-dependent dielectric breakdown (TDDB) effects degrade the device parameters, and in turn degrade the performance of the active inductors and filt... View full abstract»

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  • Transaction level modeling of an OSI-like layered NoC

    Publication Year: 2006, Page(s):404 - 408
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (287 KB) | HTML iconHTML

    The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled View full abstract»

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  • Hybrid fault simulation with compiled and event-driven methods

    Publication Year: 2006, Page(s):240 - 243
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    In this paper, we propose a method to speed-up fault simulation. The proposed method takes a hybrid approach with compiled simulation and event-driven simulation. Compiled simulation is applied for fan-out free regions (FFRs). FFRs to be simulated are selected with the event-driven manner. Since the event-driven simulation contributes to avoidance of waste simulation and the compiled simulation co... View full abstract»

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