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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)

13-17 Sept. 2006

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Displaying Results 1 - 25 of 84
  • International Symposium on Parallel Computing in Electrical Engineering - Cover

    Publication Year: 2006, Page(s): c1
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  • International Symposium on Parallel Computing in Electrical Engineering - Title

    Publication Year: 2006, Page(s):i - iii
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  • International Symposium on Parallel Computing in Electrical Engineering - Copyright

    Publication Year: 2006, Page(s): iv
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  • International Symposium on Parallel Computing in Electrical Engineering - TOC

    Publication Year: 2006, Page(s):v - ix
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  • Scientific Programming for Heterogeneous Systems - Bridging the Gap between Algorithms and Applications

    Publication Year: 2006, Page(s):3 - 8
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    High performance computing in heterogeneous environments is a dynamically developing area. A number of highly efficient heterogeneous parallel algorithms have been designed over last decade. At the same time, scientific software based on the algorithms is very much under par. The paper analyses main issues encountered by scientific programmers during implementation of heterogeneous parallel algori... View full abstract»

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  • Multi-Core Processors: New Way to Achieve High System Performance

    Publication Year: 2006, Page(s):9 - 13
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB) | HTML iconHTML

    Multi-core processors represent an evolutionary change in conventional computing as well setting the new trend for high performance computing (HPC) - but parallelism is nothing new. Intel has a long history with the concept of parallelism and the development of hardware-enhanced threading capabilities. Intel has been delivering threading-capable products for more than a decade. The move toward chi... View full abstract»

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  • Challenges to the Design of Mobile Middleware Systems

    Publication Year: 2006, Page(s):14 - 19
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    Mobile networks provide mobile users with access to computing services and resources anywhere, anytime. While each mobile device has limited resources and services, all of them, by networking, can create a powerful computing mobile platform. The role of the mobile middleware is to facilitate this platform. This paper discusses the main features of mobile networks that represent challenges to the d... View full abstract»

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  • Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly

    Publication Year: 2006, Page(s):20 - 30
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB) | HTML iconHTML

    A key aspect in the design and optimization process of high voltage apparatus is the precise simulation and geometric optimization of the electric electromagnetic field distribution on electrodes and dielectrics. Since these simulations and optimizations are rather compute intensive, the engineer demands a user friendly working environment requiring as little knowledge as possible with regard to t... View full abstract»

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  • A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments

    Publication Year: 2006, Page(s):31 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB) | HTML iconHTML

    Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decreasing voltage supplies. A newer method to speed up contemporary processors at small space increase is simultaneous multithreading (SMT). With the introduction of SMT, instruction fetch- and issue policies gained importanc... View full abstract»

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  • An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors

    Publication Year: 2006, Page(s):37 - 42
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (351 KB) | HTML iconHTML

    A good task allocation algorithm should find available processors for incoming jobs, if they exist, with minimum overhead. Due to its topological generality and flexibility the k-ary n-cube architecture has been chosen for the task allocation problem. We propose a fast and efficient isomorphic processor allocation scheme for k-ary n-cube systems by using isomorphic partitioning where the processor... View full abstract»

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  • Balanced Spatio-Temporal Data Warehouse with R-MVB, STCAT and BITMAP Indexes

    Publication Year: 2006, Page(s):43 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    In this article, we present new indexing and balancing methods used in parallel spatio-temporal data warehouse (B-PSTDW). Main motivation for designing the B-PSTDW system are unsatisfying results from exploitation of spatial data warehouse with cascaded star model indexed with aR-tree, which was used for distributed telemetric data processing (DSDW(t)). The DSDW(t) and B-PSTDW(t) services data fro... View full abstract»

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  • An Algorithm to Embed Hamiltonian Cycles in Crossed Cubes

    Publication Year: 2006, Page(s):49 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (395 KB) | HTML iconHTML

    In this paper, we study the problem of embedding a family of regularly-structured Hamiltonian cycles in a crosses cube. Since the crossed cube shows performance improvement over a regular hypercube in many aspects, we are interested in knowing whether it has the comparable capability in terms of structure embedding - specifically in this paper, the embedding of Hamiltonian cycles. It needs to be p... View full abstract»

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  • Application-Driven Development of Concurrent Packet Processing Platforms

    Publication Year: 2006, Page(s):55 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we have to trade off flexibility against costs and performance. Our methodology therefore focuses on characterizing the application domain as early as possible. With this input, we can narrow the design space to one major desi... View full abstract»

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  • Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs

    Publication Year: 2006, Page(s):62 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (334 KB) | HTML iconHTML

    This document presents the concept of integrating the SHECS (shared explicit cache system)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (thread-level parallelism-chip multiprocessing) SMP (symmetric multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with ... View full abstract»

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  • Evolutionary Multiprocessor Task Scheduling

    Publication Year: 2006, Page(s):68 - 76
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (135 KB) | HTML iconHTML

    The genetic algorithm has, to date, been applied to a wide range of problems. It is an ideal tool to solve problem in need of multiple, often interdependent requirements. This is because it has the ability to search within a large solution space while at the same time meeting criteria and constraints within the problem's boundaries. In this paper, we apply this heuristic to the problem of multipro... View full abstract»

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  • Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology

    Publication Year: 2006, Page(s):77 - 82
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    This paper concerns numerical computations in a new shared memory system architecture oriented towards systems on chip technology. Dynamically reconfigurable processor clusters which adjust at program run-time to computation and communication requirements of programs and a new data exchange method between processors - called "communication on the fly" are main assumed architectural features. They ... View full abstract»

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  • Open MP Extension for Multithreaded Computing with Dynamic SMP Processor Clusters with Communication on the Fly

    Publication Year: 2006, Page(s):83 - 88
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (143 KB) | HTML iconHTML

    This paper presents a possible extension of the Open MP library for programming parallel multithreaded computations in the architecture of dynamic SMP clusters with communication on the fly. Dynamic SMP clusters are composed of processors directly connected to the same local shared memory modules with the composition of the clusters arranged at program runtime. Inter-processor communication in suc... View full abstract»

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  • Generalised Resource Model for Parallel Instruction Scheduling

    Publication Year: 2006, Page(s):89 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB) | HTML iconHTML

    In this paper we introduce a generalised resource model for parallel instruction scheduling. This model is used to formulate the resource constraints for periodic loop schedules, which are then rewritten employing an efficient flow graph model. The generalisation leads to a significant simplification and acceleration of the painful process of modelling new resource classes, and of incorporating sp... View full abstract»

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  • Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks

    Publication Year: 2006, Page(s):95 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB) | HTML iconHTML

    The paper concerns task scheduling in dynamic SMP clusters based on the notion of moldable computational tasks. Such tasks have been used as atomic elements in program scheduling algorithms with warranty of schedule length. For program execution, a special shared memory system architecture is used. It is based on dynamic processor clusters, organized around shared memory modules by switching of pr... View full abstract»

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  • The Centisecond Two Levels Hidden Semi Markov Model (CTLHSMM)

    Publication Year: 2006, Page(s):101 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    A major deficiency of standard hidden Markov models (HMM) is that both the spectral and the prosodic feature are uniformly processed. To combine more efficiently the prosodic cues with the acoustic ones, a segmental two levels hidden Markov model has been recently studied by Suaudeau [Suaudeau 94]. In this paper, we present an adapted version of this model in which the segmental processing is repl... View full abstract»

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  • Energy Optimisation in Resilient Self-Stabilizing Processes

    Publication Year: 2006, Page(s):105 - 110
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    When performing an algorithm in the self-stabilizing model, a distributed system must achieve a desirable global state regardless of the initial state, whereas each node has only local information about the system. Depending on adopted assumptions concerning the model of simultaneous execution and scheduler fairness, some algorithms may differ in stabilization time or possibly not stabilize at all... View full abstract»

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  • Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach

    Publication Year: 2006, Page(s):111 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (137 KB) | HTML iconHTML

    At our university, we have a number of small-to-medium-size compute clusters and some technical simulations which could benefit from using several of these clusters simultaneously. To reach this goal, we discuss the formation of a "mini-grid" using a virtual private network to couple clusters on the message-passing level. This is a simple and pragmatic approach for those cases where the functional... View full abstract»

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  • Specification, Analysis and Testing of Grid Environments Using Abstract State Machines

    Publication Year: 2006, Page(s):116 - 120
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    Abstract state machines (ASM) are mathematically defined environment for high-level system design, verification and analysis. This paper presents a proposition of a hybrid approach to the specification, analysis and testing of grid middleware using ASM. This approach allows an easy integration of created specification of developed middleware with existing components of grid systems. The important ... View full abstract»

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  • A Two-Level Approach to Building a Campus Grid

    Publication Year: 2006, Page(s):121 - 126
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (143 KB) | HTML iconHTML

    The article proposes a two-layered system for distributed computation. The setup combines two different tools - Globus and Mosix - in order to harness the computing power wasted in unused student laboratories. The system is easy to set up and use. We present the results of experiments on a simple testbed, using the Google PageRank algorithm as an example task View full abstract»

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  • Complexity of Collective Communications on NoCs

    Publication Year: 2006, Page(s):127 - 133
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB) | HTML iconHTML

    The paper addresses the important issue related to communication performance of networks on chip (NoCs), namely the complexity of collective communications measured by a required number of algorithmic steps. Three NoC topologies are investigated, a ring network, Octagon and 2D-mesh, due to their easy manufacturability on a chip. The lower complexity bounds are compared to real values obtained by e... View full abstract»

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