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9th EUROMICRO Conference on Digital System Design (DSD'06)

Date Aug. 30 2006-Sept. 1 2006

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Displaying Results 1 - 25 of 101
  • 9th EUROMICRO Conference on Digital System Design - Cover

    Publication Year: 2006, Page(s): c1
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  • 9th EUROMICRO Conference on Digital System Design - Title

    Publication Year: 2006, Page(s):i - iii
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  • 9th EUROMICRO Conference on Digital System Design - Copyright

    Publication Year: 2006, Page(s): iv
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  • 9th EUROMICRO Conference on Digital System Design - TOC

    Publication Year: 2006, Page(s):v - xi
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  • Message fromthe Program Chair

    Publication Year: 2006, Page(s): xii
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  • Conference Committees

    Publication Year: 2006, Page(s):xiii - xiv
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  • The Challenges for High Performance Embedded Systems

    Publication Year: 2006, Page(s):3 - 7
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (111 KB) | HTML iconHTML

    Consumer electronics devices traditionally rely on non-programmable circuits for their "streaming" part. Recent demands on flexibility moved the balance towards the use of programmable components. However, there is a major gap between the current programmable processors and the actual requirements of applications. To bridge this gap, it is necessary to use parallel architectures consisting of mult... View full abstract»

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  • Digital RF

    Publication Year: 2006, Page(s): 8
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  • Deep Sub-100 nm Design Challenges

    Publication Year: 2006, Page(s):9 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (497 KB) | HTML iconHTML

    This paper will describe the problems in the design and development of deep sub-100 nm system LSI's and/or SoC's from different aspects. One of the most difficult problems is the large power consumption, in both active and stand-by modes. Another problem is how to improve the efficiency in the development of large scale chips and related softwares. Lithography, that has been getting harder and har... View full abstract»

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  • New Directions in Mobile Device Architectures

    Publication Year: 2006, Page(s):17 - 26
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1348 KB) | HTML iconHTML

    Mobile industry will face several disruptive changes in coming years. Emerging digital convergence will bring new exiting multifunctional products for consumers but it also put new requirements for the product development. Shift from vertical to horizontal mode will bring deep impact to the R&D of the whole mobile industry. Emerging dominant platforms and architectures will challenge the whole... View full abstract»

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  • Robustness in SOC Design

    Publication Year: 2006, Page(s):27 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    Embedded systems, ubiquitous computing and networked architectures are getting more and more important within our society. System parts are often completely implemented as integrated circuits (SoC = system on chip). Consequently, their complexity and heterogeneity have grown dramatically in the recent past. Moreover, embedded systems are used in environments where parameters are subject to continu... View full abstract»

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  • Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication

    Publication Year: 2006, Page(s):37 - 44
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (198 KB) | HTML iconHTML

    We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto network-on-chip (NoC) communication. We first identify four basic forms of NoC process interaction patterns at the process level, namely, producer-consumer, peers, client-server, and multicast. We propose a three-step top-down refinement method: channel refinement, protocol refinemen... View full abstract»

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  • Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication

    Publication Year: 2006, Page(s):45 - 52
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    Network-on-chip-based multiprocessor systems-on-chip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves scheduling the communication on the network-on-chip. This paper presents different scheduling strategies that minimize resource usage by exploiting all scheduling freedom offered by networks-on-chip. Our experime... View full abstract»

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  • On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

    Publication Year: 2006, Page(s):53 - 60
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (230 KB) | HTML iconHTML

    The concept of network on chip (NoC) is a recent breakthrough in the system on chip (SoC) design area. A lot of work has been done to define efficient NoC architectures and implementations. In this paper, our goal is twofold. Firstly, we want to outline that the use of a NoC based shared-memory multiprocessor SoC challenges the application integrator because of the underlying assumptions of softwa... View full abstract»

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  • Partition Based Dynamic 2D HW Multitasking Management

    Publication Year: 2006, Page(s):61 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB) | HTML iconHTML

    The design of computing systems is facing an interesting challenge with the opportunity to include runtime reconfigurable (RTR) devices in them. Operating systems (OS) need to be extended with functionalities that allow to efficiently manage such devices. We present a simple and fast algorithm for the management of FPGA area in a general-purpose computing system with hardware multitasking. It divi... View full abstract»

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  • Global Analysis of Resource Arbitration for MPSoC

    Publication Year: 2006, Page(s):71 - 78
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    Modern day applications require use of multi-processor systems for reasons of scalability and power efficiency. As more and more applications are integrated on a single device, mapping and analyzing them on a multi-processor system becomes a multi-dimensional problem. Each possible set of applications that can be active simultaneously leads to a different use-case (also referred to as scenario) th... View full abstract»

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  • Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering

    Publication Year: 2006, Page(s):79 - 82
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (146 KB) | HTML iconHTML

    Maintaining local caches coherent in bus-based multiprocessor systems results in significantly elevated power consumption, as the bus snooping protocols require local cache lookups for each memory reference placed on the common bus. Such a conservative approach is warranted in general-purpose systems, where no prior knowledge regarding the communication structure between threads or processes is av... View full abstract»

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  • Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA

    Publication Year: 2006, Page(s):83 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB) | HTML iconHTML

    In large system-on-chip (SoC) architectures, balancing the clock network is increasingly difficult. Globally asynchronous locally synchronous (GALS) removes the need for global clock net, and also provides efficient means for managing the complexity and re-use in large architectures. However, quantitative comparisons of GALS against similar synchronous structures are rare for full SoC architecture... View full abstract»

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  • Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization

    Publication Year: 2006, Page(s):89 - 96
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (207 KB) | HTML iconHTML

    Several techniques were developed to reduce processor consumption which was the predominant source of dissipation. However with the technology evolution and the development of new applications that make heavy use of large memory data size, the energy savings obtained by these techniques become limited. In this article we showed that dynamic voltage frequency scaling technique (DVFS) increases the ... View full abstract»

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  • A Monitoring-Aware Network-on-Chip Design Flow

    Publication Year: 2006, Page(s):97 - 106
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (185 KB) | HTML iconHTML

    Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements... View full abstract»

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  • A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing

    Publication Year: 2006, Page(s):107 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB) | HTML iconHTML

    We propose a run-time re-configurable parametric architecture (fabric) for local neighborhood image processing. The proposed architecture is composed of polymorphous cells where each cell accesses neighborhood data from a local cell memory, and executes a neighborhood function sequentially. The architecture is flexible since different neighborhood functions can be implemented by rewriting a cell's... View full abstract»

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  • A Hardware IP-Core for Information Retrieval

    Publication Year: 2006, Page(s):115 - 122
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB) | HTML iconHTML

    With the ever increasing amounts of information stored on the Web or archived within computing systems, high performance data processing architectures are required to process this data in real time. The aim of the work presented in this paper is the development of a hardware text mining IP-Core for use in FPGA based systems. In this paper we describe the development of our text processing hardware... View full abstract»

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  • Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems

    Publication Year: 2006, Page(s):123 - 126
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (137 KB) | HTML iconHTML

    The increased complexity and operating frequency in current microprocessors is resulting in a decrease in the performance improvements. In order to keep up with the expected performance gains, major manufacturers have started to offer chip-multiprocessor architectures. Nevertheless, the integration of several cores on the same chip leads to increased heat dissipation and consequently additional co... View full abstract»

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  • Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors

    Publication Year: 2006, Page(s):127 - 130
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (117 KB) | HTML iconHTML

    This paper describes the development of FPGA based co-processor architecture for accelerating vector comparisons e.g. Euclidean distance. In this paper we compare traditional pipelined and data/low implementations, in terms of processing speed and area requirements. Processing performance is compared against a software implementation to evaluate possible speedup View full abstract»

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  • Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods

    Publication Year: 2006, Page(s):131 - 138
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    During the last decade various asynchronous circuit structures and design methods have been proposed that seem to be quite different. In essence, however, all these methods contribute to solving the same fundamental design problem in one way or another. In this paper we use a simple communication model to figure out what this fundamental design problem actually is and to highlight its roots. We sh... View full abstract»

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