2006 43rd ACM/IEEE Design Automation Conference

24-28 July 2006

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  • 2006 Design Automation Conference (IEEE Cat. No. 06CH37797)

    Publication Year: 2006, Page(s): C1
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  • General Chair's welcome

    Publication Year: 2006, Page(s): i
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  • [Breaker page]

    Publication Year: 2006, Page(s): ii
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  • Table of contents

    Publication Year: 2006, Page(s):iii - xx
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  • Contributor Listings

    Publication Year: 2006, Page(s):xxi - xxii
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  • Contributor Listings

    Publication Year: 2006, Page(s):xxiii - xxiv
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  • Contributor Listings

    Publication Year: 2006, Page(s): xxv
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  • Contributor Listings

    Publication Year: 2006, Page(s): xxvi
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  • iPod or Iridium - Which one are you going to be? [Monday keynote address]

    Publication Year: 2006, Page(s): xxvii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (607 KB) | HTML iconHTML

    Summary form only given, as follows. An incredible amount of time, resources and investment is being made by EDA, chip, and electronics companies to win in the exploding multi-media, gaming, and entertainment applications markets. With the 2006 DAC conference doing a much-needed "deep dive" into how the semiconductor industry meets technical challenges, Joe Costello, Chairman of Orb Networks, Inc.... View full abstract»

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  • Structuring process and design for future mobile communication devices [general session keynote address]

    Publication Year: 2006, Page(s): xxviii
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  • [Commentary]

    Publication Year: 2006, Page(s): xxix
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  • Awards

    Publication Year: 2006, Page(s): xxx
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  • Awards

    Publication Year: 2006, Page(s): xxxi
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  • Awards

    Publication Year: 2006, Page(s): xxxii
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  • Awards

    Publication Year: 2006, Page(s): xxxiii
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  • Reviewer listings

    Publication Year: 2006, Page(s):xxxiv - xxxvii
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  • Call for papers

    Publication Year: 2006, Page(s): xxxviii
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  • Panel: how will the fabless model survive?

    Publication Year: 2006, Page(s):1 - 2
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    The fabless model was traditionally enabled through clean interfaces oth in technical and business terms - between foundries and fabless semiconductor companies. However, with advanced geometry and analog/mixed-signal process nodes, the technical challenges have been greatly magnified, so that successful semiconductor design requires intimate co-optimization of design and manufacturing, inf... View full abstract»

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  • The good, the bad, and the ugly of silicon debug

    Publication Year: 2006, Page(s):3 - 6
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB) | HTML iconHTML

    Silicon debug begins with the arrival of design prototypes and can continue well after a product has gone into production. It is perhaps the most exciting and challenging stage of the integrated circuit development process. This paper gives an overview of silicon debug, and describes tools and methods used during the debug process View full abstract»

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  • A reconfigurable design-for-debug infrastructure for SoCs

    Publication Year: 2006, Page(s):7 - 12
    Cited by:  Papers (116)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3321 KB) | HTML iconHTML

    In this paper we present a design-for-debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction ide... View full abstract»

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  • Visibility enhancement for silicon debug

    Publication Year: 2006, Page(s):13 - 18
    Cited by:  Papers (7)  |  Patents (69)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2565 KB) | HTML iconHTML

    Several emerging design-for-debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the sili... View full abstract»

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  • A CPPLL hierarchical optimization methodology considering jitter, power and locking time

    Publication Year: 2006, Page(s):19 - 24
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (4851 KB) | HTML iconHTML

    In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling of the PLL enables fast simulations and includes the important PLL performances jitter, power and locking time, as well as stability constraints for the nonlinear locking process and the linear lock-in st... View full abstract»

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  • Hierarchical bottom-up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard

    Publication Year: 2006, Page(s):25 - 30
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3394 KB) | HTML iconHTML

    This paper describes key points and experimental validation in the development of a bottom-up hierarchical, multi-objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous-time DeltaSigma A/D converter for WLAN applications, to generate a set of Pareto-optimal design solutions. The generated performance tradeoff offers the designer access to a set of o... View full abstract»

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  • Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

    Publication Year: 2006, Page(s):31 - 36
    Cited by:  Papers (28)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2807 KB) | HTML iconHTML

    Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal Pareto front efficiently using a simulator-in-a-loop approach. The solutions on this Pareto front combined with efficient Monte Carlo approximation ideas are then used... View full abstract»

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  • A real time budgeting method for module-level-pipelined bus based system using bus scenarios

    Publication Year: 2006, Page(s):37 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4490 KB) | HTML iconHTML

    In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus based system while satisfying given end-to-end real-time constraints of the entire system such as throughput and latency constraints. In this paper, we define a bus scenario representing a set of possible execution sequences... View full abstract»

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