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Junction Technology, 2006. IWJT '06. International Workshop on

Date 15-16 May 2006

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  • [Front cover]

    Publication Year: 2006 , Page(s): C1
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 1
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 1
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  • Contributor Listings

    Publication Year: 2006 , Page(s): 1 - 2
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  • [Opinion]

    Publication Year: 2006 , Page(s): 1
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  • Table of contents

    Publication Year: 2006 , Page(s): I - X
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  • MUGFET - alternative transistor architecture for 32 nm CMOS generation

    Publication Year: 2006 , Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are also presented View full abstract»

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  • China for Semiconductor Equipment Supplier

    Publication Year: 2006 , Page(s): 2
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    First Page of the Article
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  • Recent Development of Semiconductor Technology in China

    Publication Year: 2006 , Page(s): 3
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    China semiconductor industry is booming in terms of manufacturing technologies and catching up with the leading edge technologies. However, although the design capability in China has made good process but still has long way to go to meet domestic IC demands. This talk will review the most advanced semiconductor technology trend in the world and semiconductor industry development status in China. This talk will also review current status of design houses in China and their demand to semiconductor technologies including junction technologies View full abstract»

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  • 45nm Node p+ USJ Formation With High Dopant Activation And Low Damage

    Publication Year: 2006 , Page(s): 4 - 9
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6296 KB) |  | HTML iconHTML  

    We investigated various p+ extension implantation dopant species (B, BF2, B10H14 & B18H 22) and annealing techniques (spike, flash, laser and SPE) to achieve high dopant activation low damage ultra-shallow junctions (USJ) 15-20 nm deep for 45 nm node applications. New USJ metrology techniques were investigated to determine: 1) surface dopant activation level and 2) junction quality (residual implant damage) using contact and non-contact full wafer metrology methods. We discovered that using molecular dopant species (B10H14 & B18 H22) either high temperature (flash or laser) annealing or low temperature SPE annealing are very promising for the 45 nm node process integration with SiON or high-k Hf-based dielectric gate stack structures because of their wide temperature range for dopant activation without diffusion View full abstract»

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  • Shallow junctions in silicon via low thermal budget processing

    Publication Year: 2006 , Page(s): 10 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5627 KB) |  | HTML iconHTML  

    The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6times1020 cm-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800degC for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing View full abstract»

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  • Control of both number and position of dopant atoms in semiconductors by single ion implantation

    Publication Year: 2006 , Page(s): 16 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4697 KB) |  | HTML iconHTML  

    Continued challenge for higher-performance semiconductor device requires the controlled doping of single-dopant atom to control the electrical properties. Here we report the fabrication of semiconductors with both dopant number and position controlled by using a one-by-one doping technique, which we call "single-ion implantation" (SII). This technique enables us to implant dopant ions one-by-one into a fine semiconductor region until the necessary number is reached. Electrical measurements reveal that the threshold voltage (Vth) fluctuation for the ordered dopant arrays is less than for conventional random doping. We also find that the device with ordered dopant array exhibits two times the lower average value (-0.4 V) of Vth shift than the random dopant distribution (-0.2 V). We conclude that the observed lower value originates from the uniformity of electrostatic potential in the channel region due to the ordered distribution of dopant atoms. The ordered dopant arrays may increase the prospects of fluctuation-controlled advanced silicon transistors View full abstract»

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  • Precision Implant Requirements for SDE Junction Formation in sub-65 nm CMOS Devices

    Publication Year: 2006 , Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4087 KB) |  | HTML iconHTML  

    Sub-65 nm devices are becoming increasingly sensitive to variations of ion beam angular properties. Beam divergence and beam steering effects in source/drain extension (SDE) implants could significantly shift device characteristics. In this paper we review the implant precision requirements for source/drain extension (SDE) formation for sub-65 nm node devices. TCAD simulation was used to analyze the effects of beam emittance and steering errors for an on-axis (0deg) SDE implant. In addition, the effect of energy contamination introduced along with decelerated low energy ions is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state-of-the-art ultra-low energy implanters are formulated View full abstract»

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  • Minimizing Pattern Dependency in Millisecond Annealing

    Publication Year: 2006 , Page(s): 25 - 30
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6412 KB) |  | HTML iconHTML  

    Millisecond annealing is a key enabling technology for creating the ultra-shallow junctions of the 65 nm node and beyond. The very short thermal diffusion distances inherent in millisecond annealing exacerbate larger scale pattern density differences and can result in corresponding differences in annealing temperatures. This paper considers the three different methods of achieving millisecond annealing times and the various ways that pattern effects can be minimized in each case. These include opaque coatings, dummification and careful selection of the wavelength, incidence angle and polarization of the radiation used for annealing. Each method has its own set of advantages and disadvantages and these are enumerated. The article concludes with a short comparison of the results obtained with three commercially available, millisecond annealing systems View full abstract»

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  • High quality ion implanter; EXCEED3000AH-Nx for 45nm beyond I/I process<Beam Size and Angle>

    Publication Year: 2006 , Page(s): 31 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4170 KB) |  | HTML iconHTML  

    For the 45 nm beyond advanced LSI mass-production, accurate dose and beam angle control for the implantation process is highly required. For the purpose the ion beam size and angle monitor was developed and installed in EXCEEDS 000AH new version medium current ion implanter.. The measured results shows the beam size and angle increased at the beam energy decreased, especially for the Y direction beam divergence is severe. As the solution, further development items are present View full abstract»

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  • Simulating Enhanced Diffusion and Activation of Boron by Atomistic Model

    Publication Year: 2006 , Page(s): 36 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3815 KB) |  | HTML iconHTML  

    The kinetic Monte Carlo (KMC) method has been the applicable method for the investigation on annealing process. In this paper, the simulation on both enhanced diffusion and inactivation of B is presented. The inactivation and clustering of B implanted at 0.5 keV and annealed at 900degC~1200degC are correctly simulated. The model can also correctly simulate the enhanced diffusion of B introduced by ultra-low energy implantation or pre-doping. Analysis on the evolution of B-Si clusters in annealing is performed View full abstract»

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  • Maximizing Boron Activation in Solid Phase Epitaxy - A Case of Implant Choice and RTP Processing

    Publication Year: 2006 , Page(s): 40 - 43
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    Solid phase epitaxial regrowth (SPER) has been re-evaluated using molecular boron implantation techniques (B18H22) for the purpose of source/drain extensions as well as for the NFET's halo implants. It had been found that reverse annealing can be omitted. The well documented benefits of fast ramp spike temperature profiles allow the use of highly activating anneals above 800degC without significant de-activation, though extending the useful SPER temperature regime and still limiting diffusion. Typical dopant concentrations for halo implants can get significantly activated during low temperature SPER anneals for those implants View full abstract»

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  • Self-Amorphizing Gas Cluster Ion Beam Technology and Combination with Laser Spike Anneal for Highly Scaled Source Drain Junction

    Publication Year: 2006 , Page(s): 44 - 47
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    High energy borane (B2H6) gas cluster ion beam (GCIB) successfully enables a sub-10 nm box-shaped dopant profile without channeling tail, and steep gradient (2.5 nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter leakage component in p+/n-well junction was reduced compared to the conventional co-implantation process with pre-amorphization, which might come from novel self-amorphization mechanism by energized clusters without foreign impurities such as Ge and F. For further scaled devices, GCIB can provide more efficient boron activation by laser spike annealing (LSA) while maintaining the scaled extension profile by combination with the reduced temperature spike RTA View full abstract»

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  • Characteristics of ultrashallow p+/n junction prepared cluster boron (B18H22) ion implantation and excimer laser annealing

    Publication Year: 2006 , Page(s): 48 - 49
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    Ultrashallow junction (<10 nm) p+/n junction formed by B18H22 cluster ion implantation and excimer laser annealing (ELA) is demonstrated. B18H22 + equivalent implantation energy at 0.25 keV readily forms an amorphous-silicon (a-Si) layer without additional Si+ or Ge+ implantation. After ELA at 500 mJ/cm2, diffusion of the boron profile was almost negligible, which can be explained by selective melting of a-Si View full abstract»

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  • Modeling and Simulation of Fluorine Related Diffusion in Silicon

    Publication Year: 2006 , Page(s): 50 - 53
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3504 KB) |  | HTML iconHTML  

    Fluorine related diffusion has drawn extensive attention recently, for experiments revealed that co-implanted F in Si can reduce transient enhanced diffusion (TED) of boron. However, disagreement still exists on whether this effect is caused by interaction of F with point defects or that with boron atoms. Also, some unusual F diffusion behaviors are still not thoroughly understood. We attempt to establish a universal model to explain the F related diffusion. In this paper, we will present our first-principles study on F related structures. Based on results of theoretical study, we established a continuum model to simulate F related diffusion extensively, including F diffusion during solid phase epitaxy (SPE) process, F diffusion at low and high concentration levels, and boron TED suppression caused by co-doping with F. The simulation results are in good agreement with the experiments supporting different mechanisms of F related diffusion View full abstract»

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  • Molecular Dynamic Simulation on Boron Cluster Implantation for Shallow Junction Formation

    Publication Year: 2006 , Page(s): 54 - 57
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    A molecular dynamic method for cluster implantation simulation which is a potential technology for shallow junction formation in integrated circuits manufacture, aimed at microelectronics application, is presented in this paper. Accurate geometric structures of boron clusters including H atoms are described by the model. A potential function taking a form of combining the ZBL and the SW potentials is applied to model interaction among the atoms in the boron cluster. Simulations of B monomer, B10H14 and B18H22 are performed. The distributions of both B and H in monomer and cluster implantation are verified by SIMS data. It is notable that with the cluster model presented, the simulation can reproduce the difference of monomer and cluster implantation very well View full abstract»

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  • Physical Model for Surface Annihilation of Silicon Interstitials during Annealing

    Publication Year: 2006 , Page(s): 58 - 61
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3711 KB) |  | HTML iconHTML  

    Surface annihilation is the main mechanism through which implantation defects are annealed out from Si wafer. Surface annihilation possibility of silicon interstitials has obvious impact on total diffusion of dopant as well as junction depth. In this paper, a model on variation of surface annihilation possibility for silicon interstitials is proposed. By considering the surface annihilation rate and desorption rate and surface defect point, the analytical model for effective surface annihilation possibility is developed and verified. The impact of surface annihilation possibility on enhanced diffusion is simulated View full abstract»

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  • Junction Specifications for the 45nm Node

    Publication Year: 2006 , Page(s): 62 - 67
    Cited by:  Papers (1)
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    As processes are being defined and transistor architectures are being selected for the 45 nm node, the International Technology Roadmap for Semiconductors (ITRS) provides a worthwhile reference for comparing options. In this paper, we discuss those parameters of the ITRS which are related to transistor junctions, from the viewpoint of one selecting a transistor design. Any selection involves tradeoffs, so by addressing how much leeway is expected for the different targets, those selections can be simplified. Along the way, we highlight some interesting contrasts, and present some unique approaches for reaching the targets View full abstract»

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  • Device Performance Evaluation of PMOS Devices Fabricated by B2H6PIII/PLAD Process on Poly-Si Gate Doping

    Publication Year: 2006 , Page(s): 68 - 72
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    It has been shown that the PIII/PLAD poly-Si gate doping process offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. PMOS devices fabricated by a B 2H6/H2 PIII/PLAD process on P+ poly-gate doping are intensively evaluated in this paper. In addition to higher throughput, PMOS devices fabricated by a PLAD process showed an equivalent electrical performance to those fabricated by conventional beam line ion implantation, including similar poly-Si gate resistance and depletion, threshold and sub-threshold characteristics, drive current, and gate-oxide integrity View full abstract»

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  • FINFET Device Junction Formation Challenges

    Publication Year: 2006 , Page(s): 73 - 77
    Cited by:  Papers (3)  |  Patents (87)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4035 KB) |  | HTML iconHTML  

    Double-gate devices with ultra-thin body are considered the most promising for scaling into the sub-20 nm regime because of their steeper sub-threshold slope, reduced short channel effects, improved mobility, and drive current. The FinFET device structure is an attractive double-gate structure and most compatible with today's standard processing technologies. One of the challenging issues of fabricating FinFETs device is how to form the FinFET's source-drain junction in the Fin area and develop metrology techniques to measure it. In this paper, we discuss the challenges of implanting ultra-thin fins and metrology development for measuring Fin doping concentration. Our simulation results demonstrate that a high angle of implantation at a certain energy is needed to maximize the dopant distribution in the Fin. Raman microscopy has been developed as a Fin doping measurement metrology. To ease the junction diffusion under the gate and reduce off current dispersion, a gate-source/drain underlap FinFET structure is investigated to make FinFET junction formation more manufacturable. Our simulation data yields optimal characteristics and shows robustness to process variation View full abstract»

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