By Topic

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Date 6-10 March 2006

Go

Filter Results

Displaying Results 1 - 25 of 49
  • [Cover]

    Page(s): 1
    Save to Project icon | PDF file iconPDF (3595 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): ii - v
    Save to Project icon | PDF file iconPDF (42 KB)  
    Freely Available from IEEE
  • Contributor Listings

    Page(s): 1
    Save to Project icon | PDF file iconPDF (59 KB)  
    Freely Available from IEEE
  • Architectures for efficient face authentication in embedded systems

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1542 KB) |  | HTML iconHTML  

    Biometrics represents a promising approach for reliable and secure user authentication. However, they have not yet been widely adopted in embedded systems, particularly in resource-constrained devices such as cell phones and personal digital assistants (PDAs). In this paper, we investigate the challenges involved in using face-based biometrics for authenticating a user to an embedded system. To enable high authentication accuracy, we consider robust face verifiers based on principal component analysis/linear discriminant analysis (PCA-LDA) algorithms and Bayesian classifiers, and their combined use (multi-modal biometrics). Since embedded systems are severely constrained in their processing capabilities, algorithms that provide sufficient accuracy tend to be computationally expensive, leading to unacceptable authentication times. On the other hand, achieving acceptable performance often comes at the cost of degradation in the quality of results. Our work aims at developing embedded processing architectures that improve face verification speed with minimal hardware requirements and without any compromise in verification accuracy. We analyze the computational characteristics of face verifiers when running on an embedded processor, and systematically identify opportunities for accelerating their execution. We then present a range of targeted hardware and software enhancements that include the use of fixed-point arithmetic, various code optimizations, application-specific custom instructions and co-processors, and parallel processing capabilities in multi-processor systems-on-chip (SoCs). We evaluated the proposed architectures in the context of open-source face verification algorithms running on a commercial embedded processor (Xtensa from Tensilica). Our work shows that fast, in-system verification is possible even in the context of many resource-constrained embedded systems. We also demonstrate that high authentication accuracy can be achieved with minimum hardware o- - verheads, while requiring no modifications to the core face verification algorithms View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software implementation of Tate pairing over GF(2/sup m/)

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (121 KB) |  | HTML iconHTML  

    Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of such fields. We show that the choice of fields of large size to make these attacks infeasible does not lead to a degradation of the computation performance of the pairing. We describe and evaluate by simulation an implementation of the Tate pairing that allows to achieve good timing results, comparable with those reported in the literature but with a higher level of security View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of Regular Expression Pattern Matching Circuits on FPGA

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (363 KB) |  | HTML iconHTML  

    Regular expressions are widely used in network intrusion detection system (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to the speed advance of networks, many previous works propose hardware architectures on FPGA to accelerate attack detection. The challenge of hardware implementation is to accommodate the regular expressions to FPGAs of the large number of attacks. Although the minimization of logic equations has been studied intensively in the CAD area, the minimization of multiple regular expressions has been largely neglected. This paper presents an architecture allowing our algorithm to extract and share common sub-regular expressions. Experimental results show that our sharing scheme significantly reduces the area of regular expression circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    Many electronic systems contain implementations of cryptographic algorithms in order to provide security. It is well known that cryptographic algorithms, irrespective of their theoretical strength, can be broken through weaknesses in their implementation. In particular, side-channel attacks, which exploit unintended information leakage from the implementation, have been established as a powerful way of attacking cryptographic systems. All side-channel attacks can be viewed as consisting of two phases - an observation phase, wherein information is gathered from the target system, and an analysis or deduction phase in which the collected information is used to infer the cryptographic key. Thus far, most side-channel attacks have focused on extracting information that directly reveals the key, or variables from which the key can be easily deduced. We propose a new framework for performing side-channel attacks by formulating the analysis phase as a search problem that can be solved using modern Boolean analysis techniques such as satisfiability solvers. This approach can substantially enhance the scope of side-channel attacks by allowing a potentially wide range of internal variables to be exploited (not just those that are "simply" related to the key). For example, software implementations take great care in protecting secret keys through the use of on-chip key generation and storage. However, they may inadvertently expose the values of intermediate variables in their computations. We demonstrate how to perform side-channel attacks on software implementations of cryptographic algorithms based on the use of a satisfiability solver for reasoning about the secret keys from the values of the exposed variables. Our attack technique is automated, and does not require mathematical expertise on the part of the attacker. We demonstrate the merit of the proposed technique by successfully applying it to two popular cryptographic algorithms, DES and 3DES View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 830mW, 586kbps 1024-bit RSA chip design

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    This paper presents an RSA hardware design that simultaneously achieves high-performance and low-power. A bit-oriented, split modular multiplication algorithm and architecture are proposed to fully exert the radix-4 computational capability. Further, we identify the switching profile of RSA data and accordingly propose power-optimized designs for the storage elements and key computational components. The complete RSA modular exponentiation hardware has been implemented using cell-based 0.18mum CMOS technology. Post-layout simulation shows that the design delivers an average performance of 586kbps at 460MHz, 1.8Vwhile consuming only 830mW View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1348 KB) |  | HTML iconHTML  

    A debug port controller (DPC) architecture, designed for re-use in multiple system-on-chip (SoC) integrated circuits (ICs) is presented. The DPC incorporates security protection against unauthorized access along with advanced debugging features such as long chain debugging, universal BIST engines control, and generic serial interfaces. Implemented security architecture of DPC is presented together with an overall IC security scheme. DPC is the most important part of this IC security scheme. The suggested architecture demonstrates extensive use of the debug process, and re-use of the DPC in multiple SoC ICs without the need of adopting its design for a specific SoC. The implementation of the DPC for IEEE 1149.1 standard is presented and the hardware realization of the proposed architecture is described in detail. The DPC that incorporates the proposed architecture has been designed in a 90 nm CMOS process as an integral part of several SoC ICs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    Mask programmable gate arrays (MPGAs) see a growing importance because of the increase of design cost and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated field-programmable gate-array (FPGA) prototype-design into an MPGA. An automatic conversion flow is essential to success. In this paper, we present a conversion flow for a look-up table-based (LUT-based) MPGA without applying re-synthesis but preserving the gate-level netlist and reusing the placement. The resulting flow has a special routing tool and buffer insertion algorithm for timing integrity. The experimental investigations use a commercial FPGA and industrial benchmarks View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-Efficient FPGA Interconnect Design

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (878 KB) |  | HTML iconHTML  

    Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is demonstrated that the delay of a full-swing, fully-buffered interconnect architecture can be matched by a low-swing solution that dissipates significantly less power and contains a mix of buffer and pass-gate switches. The actual energy savings depend on the specifics of the interconnect design and applications involved. For the considered fine-grain FPGA example, energy savings are observed to range from a factor 4.7 for low-load critical nets to a factor 2.8 for high-load critical nets. The results are obtained from circuit simulations in a 0.13mum CMOS technology for various benchmarks View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new approach to compress the configuration information of programmable devices

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1604 KB) |  | HTML iconHTML  

    During the last decade programmable devices have gained an impressive diffusion, tackling some traditional ASIC marked domains. In particular, multi-million gates FPGAs have become a very appealing low-cost solution even for consumer applications. However, one of the big issues that can arise with modern FPGA devices is the need for large and expensive external non-volatile memory to keep the configuration data. In this work we developed an alternative technique to compress FPGA bitstreams based on the knowledge of the device internal structure. The proposed method performs a two-step coder: in the first step the bitstream is adoptively "filtered" to remove data redundancy, while in the second step an arithmetic coder is used to actually compress the information. The effectiveness of the proposed technique has been demonstrated on a set of case studies. As a result conventional approaches are outperformed reaching a compression ratio of 4.26 against 3.3 times View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computational and has an important restriction in execution time due to the requirement to get interactive results. We demonstrate that the execution of this algorithm in MorphoSys can take advantage of the available parallel resources, as well as of the possibility of one cycle configuration change. In this paper we show that it is possible to implement the rendering algorithm in our coarse grain reconfigurable architecture, obtaining values over 100 fps View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application specific instruction processor based implementation of a GNSS receiver on an FPGA

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigurable hardware macro is an ASIP accelerated by additional eFPGA and weakly configurable ASIC based co-processors. The different hardware building blocks (i.e. ASIP, eFPGA, ASIC) of the target architecture are motivated with state of the art GNSS receiver algorithms. To explore the design space of the target architecture and to develop appropriate partitioning cost functions a GNSS receiver testbed was realised on an FPGA board. The testbed utilises a programmable ASIP, designed and generated with the processor description language LISA, as a central processing unit. As a first accelerating co-processor the correlator was realised. Exemplary optimisations of the ASIP/co-processor architecture as well as the achieved improvements are described View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Methodology for FPGA to Structured-ASIC Synthesis and Verification

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (198 KB) |  | HTML iconHTML  

    Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. The most important aspects of this methodology are the use of physically identical blocks for difficult-to-verify PLLs, I/O and RAM and a structured re-synthesis of FPGA logic blocks to target cells that guarantees anchor points for easy formal verification View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of System Verilog Assertions

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (137 KB) |  | HTML iconHTML  

    In recent years, assertion-based verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip (SOC) designs. The System Verilog language integrates the specification of assertions with the hardware description. In this paper we show that there are several compelling reasons for synthesizing assertions in hardware, and present an approach for synthesizing System Verilog assertions (SVA) in hardware. Our method investigates the structure of SVA properties and decomposes them into simple communicating parallel hardware units that together act as a monitor for the property. We present a tool that performs this synthesis, and also show that the chip area required by the monitors for a industry standard ABV IP for the ARMAMBA AHB protocol is quite modest View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generating Finite State Machines from System C

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (127 KB) |  | HTML iconHTML  

    SystemC is a system level language proposed to raise the abstraction level for embedded systems design and verification. In this paper, we propose to generate finite state machines (FSM) from SystemC designs using two algorithms originally proposed for the generation of FSM from abstract state machines (ASM). This proposal enables the integration of SystemC with existing tools for test case generation from FSM. Hence, enabling two important applications: (1) using the FSM graph structure to produce test suites allowing functional testing of SystemC designs; and (2) performing conformance testing, where the FSM serves as a precise model of the observable behavior of the system used to validate lower abstraction levels of the design (e.g., register transfer level (RTL)) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Flexible Specification and Application of Rule-based Transformations in an Automotive Design Flow

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    This paper addresses an XML-based design environment, which provides a powerful basis for the manipulation of hardware design descriptions. The contribution of the paper is a flexible specification entry for the definition of transformation rules, which allows a designer to specify transformations by his/her own without having XML expertise. The specification entry provides a guided and graphically supported mechanism to define transformation rules. This opens up a new approach, in which the specification and verification of a transformation rule is carried out by using simple design examples, to be applied to arbitrary complex designs subsequently. A new key characteristic of our approach is that both transformation environment and transformation entry tool are based on a very compact definition of the hardware description language grammar in use, and both of them are fully automatically generated from that basic grammar definition. This makes our approach highly open for other hardware and system specification languages. The paper describes the transformation environment and transformation entry tool, and demonstrates its application in terms of two automotive-typical transformations, addressing power aspects on the one hand, and safety aspects on the other View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    This paper presents an innovative approach for analogue and mixed-signal verification. It consists in a "verification kit" that makes use of concepts used in state-of-art digital verification, such as automatic results collection, coverage elaboration, data checking capability, pseudo-random and constrained stimuli generation. Using a bandgap cell as case study, the paper shows as the presented approach allows a precise definition of the verification space and a saving of more than 50% of the total verification effort respect traditional verification methodologies. The paper shows also how the approach can be extended to more complex mixed-signal systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    Today almost all the people in the industry are talking widely about full chip mixed-signal simulation, both in pre-layout and post-layout conditions, basically for two main reasons: a large range of applications is moving from fully digital to mixed-signal and full chip simulation with parasitic components, together with IR drop analysis, is becoming strictly mandatory before going to silicon. In fact, the cost of a mask set for a 90nm or a 65nm technology is growing in an exponential way, passing the million dollar for any single mask set. For these reasons, it is strategic to set up a very complete mixed-signal design flow allowing designers to go to the silicon in a safe way with the minimum risk of failure. Nowadays, various approaches to the same problem are pursued by different organizations, sometimes privileging the fully digital modeling of the mixed-signal system and some other times setting the digital part in VHDL and keeping the analog part at transistor level, simulating the whole chip with a mixed-signal simulator. Which is the right approach? Which are the status and the reliability of the tools on the market ? Which is the acceptable trade-off among simulation speed, code coverage and precision of simulation results? This paper tries to answer to these questions proposing a fully qualified and complete mixed-signal flow for SoC verification, implemented to design applications also containing embedded flash memories View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software-friendly HW/SW Co-Simulation: An Industrial Case Study

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test their software with their own tools and environment using an accurate simulated ASIC (application specific integrated circuit) model. The solution presented here enables a smooth and early ASIC and SW integration, which reduces the project development time and improves the ASIC design quality (i.e., SW engineers can help in the ASIC verification and ASIC engineers can help in the SW development). In this solution, the real and full software (i.e., multi-threaded application) runs in its native environment with minimal changes and interfaces with a simulated ASIC model using sockets. We have tested this approach on a pilot-project, which has demonstrated the feasibility of this co-development methodology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling and simulation of mobile gateways interacting with wireless sensor networks

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    Sensor networks are emerging wireless technologies; their integration with the existing 2.5G, 3G mobile networks is a key issue to provide advanced services, e.g., health control. However this integration poses new challenges in the design and simulation of the involved embedded systems since it requires the cooperation of simulation tools that model hardware, software, and network aspects and their interactions. We present the modeling and simulation of a network scenario, core of a telecom provider's future portfolio, in which an ARM-based mobile handset is used as the gateway between a wireless sensor network (WSN) and remote users through a wide area network (WAN). Initially, the gateway and the WSN are modeled at system level with SystemC while the wide area network is modeled with NS-2. Then, HW/SW partitioning is performed on the gateway and an instruction set simulator of the ARM processor is used for the cycle-accurate execution of the RTOS and the application software View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Hardware-Engine for Layer-2 classification in low-storage, ultra high bandwidth environments

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    Ethernet is the most common layer-2 network protocol, and it is currently being deployed beyond the tight borders of LANs. In order to accommodate the needs of MANs and WANs, several QoS mechanisms employed at the MAC sublayer of Ethernet have been proposed. These QoS mechanisms require identification of network flows and the classification of Ethernet packets according to certain Ethernet header fields. In this paper, we propose a classification engine employed at the MAC sublayer which uses an innovative hashing scheme and internal replacement of MAC vendor IDs; the hash based classification engine (HBCE) compacts the tables containing the rules associated with certain MAC addresses and supports extremely high speed decisions - at a rate of more than 100Gb/sec -, while its memory needs are significantly lower compared to those of the similar schemes currently used. This engine has been implemented in hardware utilizing less than 0.1mm2 in a state of the art CMOS technology. As a result HBCE is a very promising candidate for the next-generation Ethernet equipments that need to support classification at data link layer at multi-gigabit per second network speeds, whereas due to its very low memory requirements and low implementation complexity, it can also be employed very efficiently in lower-bandwidth wireless environments that utilize MAC mechanisms View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIP Architecture for Multi-Standard Wireless Terminals

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (754 KB) |  | HTML iconHTML  

    This paper presents the block processing engine (BPE), an application specific instruction-set processor (ASIP) explicitly designed for the implementation of multi-standard wireless terminals. Thanks to a high level of parallelism and a consistent use of pipeline, the BPE architecture fully satisfies stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation, the physical synthesis for the CMOS 90nm STM technology and the FPGA prototyping on the ARM Versatile platform of a dual-standard frequency domain equalizer (FDE) supporting the 3GPP HSDPA and the IEEE 802.11a standards View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interconnection framework for high-throughput, flexible LDPC decoders

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1324 KB) |  | HTML iconHTML  

    This paper presents a possible interconnection structure suitable for being used in a flexible LDPC decoder. The main feature of the proposed approach is the possibility of implementing parallel or semi-parallel decoders with a reduced communication complexity. To the best of our knowledge this is the first work detailing the implementation of a fully flexible LDPC decoder, able to support any type of code. To prove the effectiveness of this approach, a complete decoder has been implemented on a XC2V8000, achieving a decoding throughput of 529 Mbps on a (1920, 640) code View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.