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2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)

Date 2-4 Aug. 2006

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Displaying Results 1 - 25 of 29
  • 2006 IEEE International Workshop on Memory Technology, Design, and Testing - Cover

    Publication Year: 2006, Page(s): c1
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  • 2006 IEEE International Workshop on Memory Technology, Design, and Testing - Title

    Publication Year: 2006, Page(s):i - iii
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  • 2006 IEEE International Workshop on Memory Technology, Design, and Testing - Copyright

    Publication Year: 2006, Page(s): iv
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  • 2006 IEEE International Workshop on Memory Technology, Design, and Testing - Table of contents

    Publication Year: 2006, Page(s):v - vii
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  • Foreword

    Publication Year: 2006, Page(s): viii
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  • Organizing Committee

    Publication Year: 2006, Page(s): ix
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  • Program Committee

    Publication Year: 2006, Page(s): x
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  • list-reviewer

    Publication Year: 2006, Page(s): xi
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  • DRAM Industry Trend

    Publication Year: 2006, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB) | HTML iconHTML

    This presentation starts with DRAM market overview, demand side DRAM bit shipment, content per box trend, followed by the DRAM density migration and the technology migration trend, including process migration, from micrometer to nanometer technology. As technology advances, 300mm fabrication and new generation products become the centerpiece of the future development of the DRAM industry. We prese... View full abstract»

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  • Roadmap of the Flash Memory

    Publication Year: 2006, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (138 KB) | HTML iconHTML

    It has become 19 years, since the development of the NAND Flash started using 0.7..m rule in 1987. The speed of the scaling has been very fast and the period of the product of the new generation is less than 2 years. Now, design rule of the NAND Flash memory has become less than 70nm. There are some problems to interfere with the scaling of the memory cell. Basic idea to overcome these problems wi... View full abstract»

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  • Non-volatile Semiconductor Memory Technology in Nanotech Era

    Publication Year: 2006, Page(s): xiv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    Non-volatile semiconductor memory, especially Flash memory has seen explosive growth in recent years because of unceasing demand for higher performance and density for cell phone, digital still camera, camcorder, MP3, consumer electronics and automotive applications. Despite the rosy outlook, both NOR and NAND Flash technologies face steep challenges to further scale down into the sub-45nm nodes. ... View full abstract»

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  • Future Prospective of Programmable Logic Non-volatile Device

    Publication Year: 2006, Page(s): xv
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    Non-Volatile Memory devices are indispensable for embedded chip/system. They are used for the storage of embedded software, which controls the operation of the chip/system. Conventionally, to embed Non-Volatile Memory devices onto a chip requires tremendous effort to develop a processing technology, which incorporates Non-Volatile Memory devices with logic devices. However, such effort requires mo... View full abstract»

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  • SRAM Design Techniques for Sub-nano CMOS Technology

    Publication Year: 2006, Page(s): xvi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB) | HTML iconHTML

    The scaling of CMOS technology has significant impacts on SRAM cell – random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM ce... View full abstract»

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  • New on-Chip DFT and ATE Features for Efficient Embedded Memory Test

    Publication Year: 2006, Page(s): xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Testing of embedded memories, independent whether it is of volatile or non-volatile type, is based on various kinds of built-in self-test. This test solution is often driven by the fact that the system application does not provide an atspeed signal interface at the product pins. In complex SoC designs it is furthermore mandatory to do BIST as there are multiple memories of various size and organiz... View full abstract»

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  • High-Quality Memory Test

    Publication Year: 2006, Page(s): xviii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (46 KB) | HTML iconHTML

    Semiconductor Companies are continuously trying to keep their customers Happy and Satisfied with new products, new functionalities and new interfaces. To keep track on inventing products with new more facilities, Semiconductor Companies have to include much more transistors per millimeter square than ever before. Nowadays, System on Chips (SoCs) are very dense, approaching 1 billion of transistors... View full abstract»

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  • Fault-pattern oriented defect diagnosis for flash memory

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    In order to ease the time-to-market pressure of flash memory, we propose a fault-pattern based diagnosis methodology that reduces the burden in yield learning. The fault-pattern based diagnosis approach is based on defect dictionary and ATE log file. The proposed diagnosis method allows product engineers to quickly isolate defect candidates. In this paper we use open/short defects to demonstrate o... View full abstract»

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  • A March-based algorithm for location and full diagnosis of all unlinked static faults

    Publication Year: 2006, Page(s):6 pp. - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    A new March-based fault location and full diagnosis algorithm is proposed for word-oriented static RAMs. A March algorithm of complexity 31N, N is the number of memory words, is defined for fault detection and partial diagnosis. Then March-like algorithms of complexity 3N to 5N are used to locate the aggressor words of coupling faults (CF) and achieve full diagnosis for all unlinked static CFs. An... View full abstract»

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  • Improved representatives for unrepairability judging and economic repair solutions of memories

    Publication Year: 2006, Page(s):6 pp. - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    This paper introduces a novel procedure of identifying better representatives of faulty cells in a memory map to help judge unrepair ability and provide economic repair recommendation. These representative faulty cells, called leading elements (LE), are classified into four primary types based on their characteristics. Three specific pairs of initially identified LE are extracted for further opera... View full abstract»

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  • A new 1T DRAM cell with enhanced floating body effect

    Publication Year: 2006
    Cited by:  Papers (3)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology has many unique characteristics, which is one of the most promising methods to the direction. As the semiconductor memory is concerned, the 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMO... View full abstract»

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  • FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

    Publication Year: 2006, Page(s):28 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    We present a ROM compiler programmable from via 1 to via n - 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. With the coding being able to take place as close to the topmost metal as possible, the turnaround time for a revision is shortened. In this paper, we discuss the array assembly scheme and its impacts on the design considerati... View full abstract»

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  • Novel memory organization and circuit designs for efficient data access in applications of 3D graphics and multimedia coding

    Publication Year: 2006, Page(s):6 pp. - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    Memory has become one of the critical components in many applications. This paper presents new designs of SRAM memory circuit and architectures for applications in 3D graphics, JPEG2000, and multimedia codec. In the 3D graphics pipeline, the memory initialization is realized by modifying the circuits in the SRAM decoder and storage cell. In the bit-plane coder (BPC) of JPEG2000, we propose a new 3... View full abstract»

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  • MRAM write error categorization with QCKBD

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3910 KB) | HTML iconHTML

    A new test pattern, quadruplet checker board (QCKBD), is proposed which enables to evaluate magnetic crosstalk from the neighbor write lines. At first, some conventional test patterns changing the write points were applied to categorize magnetic random access memory (MRAM) write errors. But magnetic crosstalk from the neighbor write lines could not be isolated by these conventional tests since mag... View full abstract»

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  • DDR2 DRAM output timing optimization

    Publication Year: 2006, Page(s):6 pp. - 54
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    The speed of DRAMs is increasing from generation to generation. This paper gives an overview of typical DRAM output timing challenges. Tight output timing specifications in the order of several 100ps are presented. Specification requirements lead to efforts to improve the output driver design. A systematic test strategy evaluates limits of automatic test equipment (ATE) overall timing accuracy (OT... View full abstract»

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  • Dynamic data stability in SRAM cells and its implications on data stability tests

    Publication Year: 2006
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    The paper discusses the concept of dynamic data stability in the SRAM cells. It is shown that the criteria for the absolute static data stability in an SRAM cell is a sub-set of its dynamic data stability. Hence, test methods that are based on dynamic stress of the cell have limited success in discovering the defective cells. Hammer test, for example, fails to discover the faults in an SRAM cell w... View full abstract»

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  • SRAM cell current in low leakage design

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (506 KB) | HTML iconHTML

    This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mum 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by... View full abstract»

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