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Sixth International Conference on Application of Concurrency to System Design (ACSD'06)

28-30 June 2006

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  • Sixth International Conference on Application of Concurrency to System Design - Cover

    Publication Year: 2006, Page(s): c1
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  • Sixth International Conference on Application of Concurrency to System Design - Title Page

    Publication Year: 2006, Page(s):i - iii
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  • Sixth International Conference on Application of Concurrency to System Design - Copyright

    Publication Year: 2006, Page(s): iv
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  • Sixth International Conference on Application of Concurrency to System Design - Table of contents

    Publication Year: 2006, Page(s):v - vii
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  • Foreword

    Publication Year: 2006, Page(s): viii
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  • Conference Organizers and Steering Committee

    Publication Year: 2006, Page(s): ix
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  • Program Committee

    Publication Year: 2006, Page(s): x
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  • Referees

    Publication Year: 2006, Page(s): xi
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  • Simulation and Verification of Asynchronous Systems by means of a Synchronous Model

    Publication Year: 2006, Page(s):3 - 14
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    Synchrony and asynchrony are commonly opposed to each other. Now, in embedded applications, actual solutions are often situated in between, with synchronous processes composed in a partially asynchronous way. Examples of such intermediate solutions are GALS, quasi-synchronous periodic processes, deadline-driven task scheduling. In this paper, we illustrate the use of the synchronous paradigm to mo... View full abstract»

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  • Communicating with Synchronized Environments

    Publication Year: 2006, Page(s):15 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB) | HTML iconHTML

    In the modern design environments, different modules, available in existent libraries, may obey different architectural styles and execution models. Reaching a well-behaved composition of such modules is a very important task of the system designer. In the framework of the action systems formalism, we analyze the co-existence of two models of execution, one synchronized, the other, interleaved. We... View full abstract»

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  • Throughput Analysis of Synchronous Data Flow Graphs

    Publication Year: 2006, Page(s):25 - 36
    Cited by:  Papers (97)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (353 KB) | HTML iconHTML

    Synchronous data flow graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities... View full abstract»

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  • On process-algebraic verification of asynchronous circuits

    Publication Year: 2006, Page(s):37 - 46
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    This paper develops a theoretical basis for using process algebra and associated model checking tools to verify asynchronous circuits. We extend existing verification theory for asynchronous circuits, and integrate it into the framework of standard process algebra theory. Our theory permits analysis of safeness (i.e. choke) and progress (i.e. illegal stop, divergence and relative starvation) condi... View full abstract»

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  • On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs

    Publication Year: 2006, Page(s):47 - 56
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    Signal transition graphs (STGs) are a popular formalism for the specification of asynchronous circuits. A necessary condition for the implementability of an STG is the existence of a consistent and complete state encoding. For an important subclass of STGs, the marked graph STGs, we show that checking consistency is polynomial, but checking the existence of a complete state coding is co-NP-complet... View full abstract»

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  • Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings

    Publication Year: 2006, Page(s):57 - 68
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    A combined framework for the resolution of encoding conflicts in STG unfoldings is presented, which extends previous work by incorporating concurrency reduction in addition to signal insertion. Furthermore, a novel validity condition is proposed to justify these transformations. The method has been implemented in the CONFRES tool and applied to a number of case studies. The experimental results sh... View full abstract»

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  • Schedulability Analysis of Petri Nets Based on Structural Properties

    Publication Year: 2006, Page(s):69 - 78
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    A schedule of a Petri net (PN) represents a set of firing sequences that can be infinitely repeated within a bounded state space, regardless of the outcomes of the nondeterministic choices. Schedulability analysis for a given PN answers the question whether a schedule exists in the reachability space of this net. This paper suggests a novel approach for schedulability analysis based solely on PN s... View full abstract»

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  • High-level Synthesis for Highly Concurrent Hardware Systems

    Publication Year: 2006, Page(s):79 - 90
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB) | HTML iconHTML

    This paper presents new approaches for high-level synthesis of highly concurrent hardware systems modeled with timed marked graphs. Unlike control data flow graphs (CDFGs) used in most high-level synthesis works, timed marked graphs can easily express highly concurrent hardware systems, including those with pipelined and multithreading behaviors. We first propose both exact and heuristic schedulin... View full abstract»

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  • Extended Timed Automata and Time Petri Nets

    Publication Year: 2006, Page(s):91 - 100
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (337 KB) | HTML iconHTML

    Timed automata (TA) and time Petri nets (TPN) are two well-established formal models for real-time systems. Recently, a linear transformation of TA to TPNs preserving reachability properties and timed languages has been proposed, which does however not extend to larger classes of TA which would allow diagonal constraints or more general resets of clocks. Though these features do not add expressive... View full abstract»

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  • In this work, we propose two translations: one from extended

    Publication Year: 2006, Page(s):101 - 110
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    We study the monitoring and fault-diagnosis problems for dense-time real-time systems, where observers (monitors and diagnosers) have access to digital rather than analog clocks. Analog clocks are infinitely-precise, thus, not implementable. We show how, given a specification modeled as a timed automaton and a timed automaton model of the digital clock, a sound and optimal (i.e., as precise as pos... View full abstract»

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  • On-the-fly TCTL model checking for Time Petri Nets using state class graphs

    Publication Year: 2006, Page(s):111 - 122
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    This paper shows how to efficiently model check a subclass of TCTL properties for the TPN model, using the so called state class method. The idea is to put the TPN model under analysis in parallel with a special TPN to capture relevant time events to verify a timed property. The special TPN, we call alarm-clock, has two transitions, with special firing priorities, which can be set to fire at speci... View full abstract»

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  • Strategies for Optimised STG Decomposition

    Publication Year: 2006, Page(s):123 - 132
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    When synthesising an asynchronous circuit from an STG, one often encounters the state explosion problem. In order to alleviate this problem one can decompose the STG into smaller components. This paper deals with the decomposition method of (W. Vogler et al., 2005), (W. Vogler et al., 2002) and introduces several strategies for efficient implementations, proves them correct and compares them by me... View full abstract»

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  • Minimal Counterexamples in O(n log n) Memory and O(n^2) Time

    Publication Year: 2006, Page(s):133 - 142
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    This article presents a new algorithm for finding a minimal counterexample in explicit state model checking with Buchi automata. The algorithm is an interleaved breadth-first search that explores some transitions backwards. We prove the correctness of our algorithm, along with complexity results. The worst-case time consumption of a simple version of our algorithm is proportional to the number of ... View full abstract»

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  • Verifying Stochastic Well-formed Nets with CSL Model-Checking Tools

    Publication Year: 2006, Page(s):143 - 152
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB) | HTML iconHTML

    Model-checking algorithms for continuous stochastic logic (CSL) properties have been introduced to facilitate the verification of stochastic systems against a variety of formally-defined performance indices. In this paper, we consider the application of CSL model-checking methods and tools to stochastic well-formed nets (SWN), a colored extension of stochastic Petri nets (SPN). Our approach is to ... View full abstract»

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  • Modelling Mobility with UML2.0 and PEPA Nets

    Publication Year: 2006, Page(s):153 - 164
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB) | HTML iconHTML

    We show how UML2.0 together with PEPA nets can be used to model dynamic aspects of mobile applications. UML2.0 provides a new form of high-level description of interactions called interaction overview diagram. The combination of interaction overview diagrams and sequence diagrams is naturally translated into PEPA nets, a performance modelling language. In this way, the designers using UML can anal... View full abstract»

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  • Models of Computation for Networks on Chip

    Publication Year: 2006, Page(s):165 - 178
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (937 KB) | HTML iconHTML

    Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making the implementation of these services entirely irrelevant for system design, an effective separation of system design from component design can be achieved. We discuss the principles to formulate network-on-chip services ... View full abstract»

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  • Modelling and verification of authentication using enhanced net semantics of SPL (Security Protocol Language)

    Publication Year: 2006, Page(s):179 - 188
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    This paper proposes an enhanced translation of Security Protocol Language (SPL) in high-level Petri nets in order to allow to prove automatically, using model-checking techniques, the authentication property of Needham-Schroeder-Lowe (NSL) protocol. The proposed approach generates finite nets and goes this way beyond the limitation which was imposed by the previous semantics due to the treatment o... View full abstract»

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