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33rd International Symposium on Computer Architecture (ISCA'06)

Date 17-21 June 2006

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Displaying Results 1 - 25 of 44
  • 33rd International Symposium on Computer Architecture - Cover

    Publication Year: 2006, Page(s): c1
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  • 33rd International Symposium on Computer Architecture - Title Page

    Publication Year: 2006, Page(s):i - iii
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  • 33rd International Symposium on Computer Architecture - Copyright

    Publication Year: 2006, Page(s): iv
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  • 33rd International Symposium on Computer Architecture - Table of contents

    Publication Year: 2006, Page(s):v - ix
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  • Message from the General Chair

    Publication Year: 2006, Page(s): x
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  • Message from the Program Chair

    Publication Year: 2006, Page(s): xi
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  • Officers

    Publication Year: 2006, Page(s): xii
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  • list-reviewer

    Publication Year: 2006, Page(s): xiv
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  • Guidelines for SIGARCH Sponsored Conferences

    Publication Year: 2006, Page(s): xvii
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  • Computer architecture research and future microprocessors: Where do we go from here?

    Publication Year: 2006, Page(s): 2
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  • A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

    Publication Year: 2006, Page(s):4 - 15
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    Packet-based on-chip networks are increasingly being adopted in complex system-on-chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These network-on-chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint and consume as little energy as possible. Further, reliability is rapidly becoming a major challenge i... View full abstract»

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  • The BlackWidow High-Radix Clos Network

    Publication Year: 2006, Page(s):16 - 28
    Cited by:  Papers (53)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB) | HTML iconHTML

    This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32Kprocessors with a worst-case diameter of seven hops, and the underlying high-radix router micro architecture and its implementation. By using a high-radix router with many narrow channels we are able to take advantage of the higher pin d... View full abstract»

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  • Memory Model = Instruction Reordering + Store Atomicity

    Publication Year: 2006, Page(s):29 - 40
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    We present a novel framework for defining memory models in terms of two properties: thread-local instruction reordering axioms and store atomicity, which describes inter-thread communication via memory. Most memory models have the store atomicity property, and it is this property that is enforced by cache coherence protocols. A memory model with store atomicity is serializable; there is a unique g... View full abstract»

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  • Conditional Memory Ordering

    Publication Year: 2006, Page(s):41 - 52
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by executing a memory barrier instruction, ensuring that recent writes have been ordered with respect to other processors in the system. We show that this model leads to superfluous memory barriers in programs with acquire-r... View full abstract»

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  • Architectural Semantics for Practical Transactional Memory

    Publication Year: 2006, Page(s):53 - 65
    Cited by:  Papers (25)  |  Patents (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (350 KB) | HTML iconHTML

    Transactional memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional state buffering and conflict resolution. Missing is a robust hardware/software interface, not limited to simplistic instructions defining transaction boundaries. Without rich semantics, current TM systems cannot support basic ... View full abstract»

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  • Ensemble-level Power Management for Dense Blade Servers

    Publication Year: 2006, Page(s):66 - 77
    Cited by:  Papers (75)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    One of the key challenges for high-density servers (e.g., blades) is the increased costs in addressing the power and heat density associated with compaction. Prior approaches have mainly focused on reducing the heat generated at the level of an individual server. In contrast, this paper proposes power efficiencies at a larger scale by leveraging statistical properties of concurrent resource usage ... View full abstract»

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  • Techniques for Multicore Thermal Management: Classification and New Exploration

    Publication Year: 2006, Page(s):78 - 88
    Cited by:  Papers (111)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB) | HTML iconHTML

    Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has examined microarchitectural policies for reducing total chip power, but these techniques alone are insufficient if not aimed at mitigating individual hotspots. The industry's trend has been toward multicore architectures, wh... View full abstract»

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  • SODA: A Low-power Architecture For Software Radio

    Publication Year: 2006, Page(s):89 - 101
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB) | HTML iconHTML

    The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or software defined radio, has a ... View full abstract»

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  • An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors

    Publication Year: 2006, Page(s):102 - 113
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (523 KB) | HTML iconHTML

    This paper presents a high-availability system architecture called INDRA $an integrated framework for dependable and revivable architecture that enhances a multicore processor (or CMP) with novel security and fault recovery mechanisms. INDRA represents the first effort to create remote attack immune, self-healing network services using the emerging multicore processors. By exploring the property o... View full abstract»

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  • Multiple Instruction Stream Processor

    Publication Year: 2006, Page(s):114 - 127
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    Microprocessor design is undergoing a major paradigm shift towards multi-core designs, since performance gains come from exploiting thread-level parallelism in the software. To support this trend, we present a novel processor architecture called the multiple instruction stream processing (MISP) architecture. MISP introduces the sequencer as a new category of architectural resource, and defines a c... View full abstract»

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  • The end of scaling? Revolutions in technology and microarchitecture as we pass the 90 nanometer node

    Publication Year: 2006, Page(s): 128
    Cited by:  Papers (1)
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  • Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

    Publication Year: 2006, Page(s):130 - 141
    Cited by:  Papers (22)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (655 KB) | HTML iconHTML

    Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocess... View full abstract»

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  • Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification

    Publication Year: 2006, Page(s):142 - 154
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order microprocessor. The conventional approach of using cross-checked load queue and store queue, while very effective in earlier processor incarnations, suffers from scalability problems in modern high-frequency designs that rely on buffering many in-flight instructions to exploit instruction-level parallelism... View full abstract»

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  • Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches

    Publication Year: 2006, Page(s):155 - 166
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    Level one cache normally resides on a processor's critical path, which determines the clock frequency. Direct-mapped caches exhibit fast access time but poor hit rates compared with same sized set-associative caches due to non-uniform accesses to the cache sets, which generate more conflict misses in some sets while other sets are underutilized. We propose a technique to reduce the miss rate of di... View full abstract»

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  • A Case for MLP-Aware Cache Replacement

    Publication Year: 2006, Page(s):167 - 178
    Cited by:  Papers (52)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache misses in parallel is called memory level parallelism (MLP). MLP is not uniform across cache misses - some misses occur in isolation while some occur in parallel with other misses. Isolated misses are more costly on perfor... View full abstract»

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