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International Conference on Dependable Systems and Networks (DSN'06)

Date 25-28 June 2006

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Displaying Results 1 - 25 of 79
  • International Conference on Dependable Systems and Networks - Cover

    Publication Year: 2006, Page(s): c1
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  • International Conference on Dependable Systems and Networks - Title Page

    Publication Year: 2006, Page(s):i - iii
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  • International Conference on Dependable Systems and Networks - Copyright

    Publication Year: 2006, Page(s): iv
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  • Table of Contents - 2006 International Conference on Dependable Systems and Networks

    Publication Year: 2006, Page(s):v - x
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  • Welcome Message from the General Chair

    Publication Year: 2006, Page(s): xi
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  • Welcome Message from the Conference Coordinator

    Publication Year: 2006, Page(s): xii
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  • Conference organizers

    Publication Year: 2006, Page(s): xiii
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  • Message from the Dependable Computing and Communications Symposium (DCCS) Program Chair

    Publication Year: 2006, Page(s): xv
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  • DCCS Program Committee

    Publication Year: 2006, Page(s): xvi
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  • List of Reviewers for DCCS

    Publication Year: 2006, Page(s): xvii
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  • William C. Carter Award

    Publication Year: 2006, Page(s): commentary
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  • Message from the Performance and Dependability Symposium (PDS) Program Chair

    Publication Year: 2006, Page(s): xx
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (33 KB) | HTML iconHTML

    Summary form only given. Since 1995, the Performance and Dependability Symposium (PDS) has been a high-quality international forum for researchers and practitioners to report on the state-of-the-art of the evaluation of the impact of faults on the operation and performance of computer and communication systems. Where in the early years of PDS the considered faults were typically accidental (hardwa... View full abstract»

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  • PDS Program Committee

    Publication Year: 2006, Page(s): xxi
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  • List of Reviewers for PDS

    Publication Year: 2006, Page(s): xxii
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  • Delivering Dependability: A Moving Target

    Publication Year: 2006, Page(s): xxiii
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  • Efficient High Hamming Distance CRCs for Embedded Networks

    Publication Year: 2006, Page(s):3 - 12
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB) | HTML iconHTML

    Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techniques. 24- and 32-bit CRC computations are becoming necessary to provide sufficient error detection capability (Hamming distance) for critical embedded network applications. However, the computational cost of such CRCs ca... View full abstract»

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  • Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors

    Publication Year: 2006, Page(s):13 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB) | HTML iconHTML

    Code and data duplication has been identified as one of the important mechanisms for improving reliability. In a chip multiprocessor-based execution environment, while it is possible to hide the overhead of code duplication through parallelism, hiding the memory space overhead incurred by data duplication is more difficult. This paper presents a compiler-directed memory-conscious data duplication ... View full abstract»

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  • Static Analysis to Enforce Safe Value Flow in Embedded Control Systems

    Publication Year: 2006, Page(s):23 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (265 KB) | HTML iconHTML

    Embedded control systems consist of multiple components with different criticality levels interacting with each other. For example, in a passenger jet, the navigation system interacts with the passenger entertainment system in providing passengers the distance-to-destination information. It is imperative that failures in the non-critical subsystem should not compromise critical functionality. This... View full abstract»

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  • The Startup Problem in Fault-Tolerant Time-Triggered Communication

    Publication Year: 2006, Page(s):35 - 44
    Cited by:  Papers (6)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB) | HTML iconHTML

    Fault-tolerant time-triggered communication relies on the synchronization of local clocks. The startup problem is the problem of reaching a sufficient degree of synchronization after power-on of the system. The complexity of this problem naturally depends on the system assumptions. The system assumptions in this paper were compiled from cooperation with partners in the automotive and aeronautic in... View full abstract»

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  • A Reconfigurable Generic Dual-Core Architecture

    Publication Year: 2006, Page(s):45 - 54
    Cited by:  Papers (6)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (281 KB) | HTML iconHTML

    In this paper we propose a generic frame for the implementation of a dual-core processor with two modes of operation. One is the safety mode that allows to run the two cores in lock step in a classical master/checker fashion. A clock delay of 1.5 clock cycles between master and checker establishes the temporal redundancy to minimize the potential for common mode faults. The second operation mode a... View full abstract»

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  • A Dependable System Architecture for Safety-Critical Respiratory-Gated Radiation Therapy

    Publication Year: 2006, Page(s):55 - 60
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    This experience report describes the design and implementation of safety-critical software and hardware for respiratory gating of a medical linear accelerator. Respiratory gating refers to a radiotherapy technique for treating cancer in the lung, liver, and abdomen, where tumors move while a patient breathes. A computer software program tracks the position of the tumor within the human body using ... View full abstract»

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  • User Interface Defect Detection by Hesitation Analysis

    Publication Year: 2006, Page(s):61 - 72
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    Delays and errors are the frequent consequences of people having difficulty with a user interface. Such delays and errors can result in severe problems, particularly for mission-critical applications in which speed and accuracy are of the essence. User difficulty is often caused by interface-design defects that confuse or mislead users. Current techniques for isolating such defects are time-consum... View full abstract»

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  • Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures

    Publication Year: 2006, Page(s):73 - 82
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB) | HTML iconHTML

    Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. Correct operation of the memory system is defined by the memory consistency model. Errors can therefore ... View full abstract»

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  • Automatic Instruction-Level Software-Only Recovery

    Publication Year: 2006, Page(s):83 - 92
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (721 KB) | HTML iconHTML

    As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically addressed reliability issues by adding redundant hardware, but these techniques are often too expensive to be used widely. Software-only reliability techniques have shown promise in their ability to protect against soft-err... View full abstract»

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  • Exploring Fault-Tolerant Network-on-Chip Architectures

    Publication Year: 2006, Page(s):93 - 104
    Cited by:  Papers (61)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB) | HTML iconHTML

    The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analysis of these reliability hazards and the incorporation of comprehensive protection measures into all network-on... View full abstract»

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