Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)

14-16 June 2006

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  • Seventeenth IEEE International Workshop on Rapid System Prototyping - Cover

    Publication Year: 2006, Page(s): c1
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  • Seventeenth IEEE International Workshop on Rapid System Prototyping - Title

    Publication Year: 2006, Page(s):i - iii
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  • Seventeenth IEEE International Workshop on Rapid System Prototyping -Copyright

    Publication Year: 2006, Page(s): iv
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  • Seventeenth IEEE International Workshop on Rapid System Prototyping - TOC

    Publication Year: 2006, Page(s):v - vii
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  • Message from the General Chairs

    Publication Year: 2006, Page(s): viii
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  • Message from the Organizing Chair

    Publication Year: 2006, Page(s): ix
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  • Message from the Program Chairs

    Publication Year: 2006, Page(s): x
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  • Acknowledgments

    Publication Year: 2006, Page(s): xi
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  • Conference Committees

    Publication Year: 2006, Page(s): xii
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  • Dynamic Mapping of Runtime Information Models for Debugging Embedded Software

    Publication Year: 2006, Page(s):3 - 9
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB) | HTML iconHTML

    Model based development based on different domain specific tools and graphical notations gains increasing importance in system design of embedded electronic systems allowing fast concept-oriented prototyping from model to code. This paper describes an extension to our seamless model based development approach: An architecture for debugging models that are executed on target systems or in dedicated... View full abstract»

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  • Principles for System Prototype and Verification Using Metamodel Based Transformations

    Publication Year: 2006, Page(s):10 - 17
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB) | HTML iconHTML

    Using domain specific modeling (DSM) allows solutions to be expressed in the idiom and at the level of abstraction of the problem domain. However, this does not imply that prototypes can be easily and rapidly generated. In reality, domain specific languages (DSLs) are difficult to design, implement and maintain, and usually there is a potential loss of efficiency when compared with hand-coded soft... View full abstract»

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  • Creation and Validation of Embedded Assertion Statecharts

    Publication Year: 2006, Page(s):17 - 23
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process for the development and verification of statechart prototype models augmented with statechart assertions using the StateRover tool. The novel aspects of the proposed process include (1) writing formal specifications using ... View full abstract»

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  • Early Embedded Software Design Space Exploration Using UML-Based Estimation

    Publication Year: 2006, Page(s):24 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: platform-based Design, which maximizes the reuse of components; and model driven development, which rises the abstraction level by using object-oriented concepts and UML. However, with this increasing of the abstraction level, software engineers do not have an exact idea... View full abstract»

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  • A Prototyping Tool for Analysis and Modeling of Video Transmission Traces over IP Networks

    Publication Year: 2006, Page(s):33 - 39
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    In the best-effort IP network, packet delay/loss is inevitably degrade the perceptual quality of real-time multimedia service, such as Voice-over-IP (VoIP), video-on-demand (VoD), etc. Modeling, prototyping, and analysis of traffic traces have always been very important and challenging topics in the area of multimedia communication. In general, packet loss/delay exhibits temporal dependence. Diffe... View full abstract»

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  • Rapid Resource-Constrained Hardware Performance Estimation

    Publication Year: 2006, Page(s):40 - 46
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology an... View full abstract»

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  • Rapid Performance and Power Consumption Estimation Methods for Embedded System Design

    Publication Year: 2006, Page(s):47 - 53
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    As embedded systems increase in complexity, rapid performance estimation methods, appropriate for use early in the design process, are becoming more and more necessary. These methods can produce significant decreases in execution time, power consumption and system cost. However, to be practicable, a design space exploration (DSE) process must be capable of evaluating several design alternatives qu... View full abstract»

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  • Performance Evaluation of an Adaptive FPGA for Network Applications

    Publication Year: 2006, Page(s):54 - 62
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of the packet's payload (DES encryption and Lempel-Ziv Compression). The co-processors can be connected either directly to the processors o... View full abstract»

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  • A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment

    Publication Year: 2006, Page(s):63 - 68
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed S... View full abstract»

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  • Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach"

    Publication Year: 2006, Page(s):69 - 75
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    This paper describes our experience in using the POSIX API standard for MPSoC applications prototyping on a reconfigurable multiprocessor ARM architecture. Applications running on this platform use a symmetric multiprocessor (SMP) POSIX compliant kernel named MUTEK. This work allows us to investigate and understand the complexities of the hardware/software interface design process. We propose a ne... View full abstract»

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  • The Prototyping Methodology of a Data Receiver for Digital Audio Broadcasting (DAB) Networks

    Publication Year: 2006, Page(s):76 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB) | HTML iconHTML

    In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over digital audio broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a personal computer via an USB port. We have implemented the system on an FPGA with an embedded RISC processor. We also d... View full abstract»

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  • System-on-Chip Design Methodology for a Statistical Coder

    Publication Year: 2006, Page(s):82 - 90
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    In this paper, we propose a system-on-chip software hardware co-design methodology for a statistical coder. We use the context adaptive binary arithmetic coder (CABAC) used in the main profile of the H.264/AVC video coding standard as a design example. The design methodology first involves performance and complexity analyses of the existing CABAC reference software, and thus the top-level CABAC so... View full abstract»

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  • Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment

    Publication Year: 2006, Page(s):91 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for... View full abstract»

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  • Asynchronous Assertion Monitors for multi-Clock Domain System Verification

    Publication Year: 2006, Page(s):98 - 102
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    PSL is a standard formal language to specify logic and temporal properties in a declarative style, under the form of assertions. We defined a library of components, and an interconnection method to automatically synthesize hardware monitors that can be linked to a prototype of the design under verification, thus providing an efficient debugging platform. The existing tool produces on-line checkers... View full abstract»

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  • Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter

    Publication Year: 2006, Page(s):103 - 109
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and ... View full abstract»

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  • Integrated Verification Approach during ADL-Driven Processor Design

    Publication Year: 2006, Page(s):110 - 118
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    Nowadays, architecture description languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of application specific instruction-set processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are on... View full abstract»

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