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36th International Symposium on Multiple-Valued Logic (ISMVL'06)

17-20 May 2006

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  • 36th International Symposium on Multiple-Valued Logic - Cover

    Publication Year: 2006, Page(s): c1
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  • 36th International Symposium on Multiple-Valued Logic - Title

    Publication Year: 2006, Page(s):i - iii
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  • 36th International Symposium on Multiple-Valued Logic - Copyright

    Publication Year: 2006, Page(s): iv
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  • 36th International Symposium on Multiple-Valued Logic - Table of contents

    Publication Year: 2006, Page(s):v - vii
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  • Message from the Symposium Chairs

    Publication Year: 2006, Page(s): viii
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  • Message from the Program Chair

    Publication Year: 2006, Page(s): ix
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  • Organizing Committee

    Publication Year: 2006, Page(s): x
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  • List of reviewers

    Publication Year: 2006, Page(s): xi
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  • Design Methods for Multiple-Valued Input Address Generators

    Publication Year: 2006, Page(s): 1
    Cited by:  Papers (14)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory. View full abstract»

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  • Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

    Publication Year: 2006, Page(s): 2
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4976 KB) | HTML iconHTML

    This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing po... View full abstract»

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  • On Designs of Radix Converters Using Arithmetic Decompositions

    Publication Year: 2006, Page(s): 3
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware... View full abstract»

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  • New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design

    Publication Year: 2006, Page(s): 4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    This paper presents an asynchronous encoding scheme using a MVL(Multi-Value Logic). This scheme reduces not only the number of wires but also the switching activities. It is achieved by the two proposed data encoding methods, RT/NRT(Return to Ternary/ Non Return to Ternary) encoding and hybrid ternary one. Conventional ternary encoding makes all data lines to intermediate to generate completion si... View full abstract»

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  • Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic

    Publication Year: 2006, Page(s): 5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise reduction. Since a dual-rail complementary duplication is performed by using two differential-pair circuits (DPCs), noise effect is distributed to only one DPC, if common-mode noise is applied to dual-rail input lines. The dual-rail complementary duplicated DPCs makes noise effect reduced, because o... View full abstract»

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  • Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

    Publication Year: 2006, Page(s): 6
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    This paper presents an evaluation of multiple-valued packet multiplexing scheme for a Network-on-Chip (NoC) architecture. In the NoC architecture, data is transferred from one Processing Element (PE) to another PE through the routers in the form of a packet. A router, suitable for both the binary and the multiple-valued packets, is constructed using the Multiple Valued Source-Coupled Logic circuit... View full abstract»

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  • On the Ranges of Algebraic Functions in Lattices - A Preliminary Report

    Publication Year: 2006, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    We investigate ranges of ternary algebraic functions in lukasiewicz-Moisil algebras, where we give a characterization of algebraic functions whose ranges are intervals and we retrieve a canonical form of functions over three-element ternary lukasiewicz-Moisil algebras, a result due to Gr. C. Moisil, one of the founders of switching theory [Moi57]. In the second part of this paper we show that in a... View full abstract»

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  • Upper and Lower Bounds on the Number of Disjunctive Forms

    Publication Year: 2006, Page(s): 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    We evaluate the upper and lower bounds on the number of disjunctive (normal) forms of an n-variable Boolean function (for our purpose it is sufficient to take the constant 1 function which always takes the value 1). We use a one-to-one correspondence between the disjunctive forms and the antichains in the ternary n-cube which is isomorphic to the partially ordered set formed by all terms of the gi... View full abstract»

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  • Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta

    Publication Year: 2006, Page(s): 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    All first-order G¨odel logics GV with globalization operator based on truth value sets V C [0,1] where 0 and 1 lie in the perfect kernel ofV are axiomatized by Ciabattoni’s hypersequent calculus HGIF [10]. View full abstract»

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  • Assumption based multi-valued semantics for extended logic programs

    Publication Year: 2006, Page(s): 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    The paper presents an approach for handling uncertain information in extended logic programs using multi-valued logics defined by bilattices. Uncertainty means that the atoms may be assigned logical values other than the conventional ones - true and false, in the semantics of the program. The logical values represent various degrees of truth, which may be combined and propagated by applying the pr... View full abstract»

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  • Implementation of Multiple-Valued CAM Functions by LUT Cascades

    Publication Year: 2006, Page(s): 11
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    In this paper, we introduce three types of multiplevalued content-addressable memories (CAMs): ordinary CAMs (CAMs), distance d CAMs, and *CAMs. Ordinary CAMs require an exact match, while *CAMs allow wildcard matches. In a distance d CAM, a match occurs even if at most d digits differ. Then, we define multiple-valued CAM functions represented by these CAMs. Next, we show an approach to realize ea... View full abstract»

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  • The new architecture of radix-4 Chinese abacus adder

    Publication Year: 2006, Page(s): 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35µm, 0.25&#... View full abstract»

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  • Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit

    Publication Year: 2006, Page(s): 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VLSI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)- based threshold logic gate, a dynamic latch and a switch block. The threshold logic gate consists of only one universal com... View full abstract»

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  • Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits

    Publication Year: 2006, Page(s): 14
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    New four-valued logic and static storage components using differential-pair circuits (DPCs) are proposed for a high-performance microprocessor datapath. The DPCbased circuit makes a signal-voltage swing small yet the current-driving capability large, and generates complementary outputs. Both a four-valued comparator and a binary static latch can be merged into a simple DPC-based circuit structure,... View full abstract»

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  • A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors

    Publication Year: 2006, Page(s): 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    In this work some Multi-Valued Logic (MVL) blocks are initially presented and they will be used to the final building of a Quaternary half-adder. A circuit equivalent to an Exclusive-OR binary gate from the binary world but working for the quaternary world is performed. Also, other basic gates are necessary like the shifter circuit, equivalent to the Not gate of the binary world, and the switching... View full abstract»

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  • Signal Processing Algorithms and Multiple-Valued Logic Design Methods

    Publication Year: 2006, Page(s): 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Multiple-valued logic can be viewed as an alternative approach to solving many problems in transmission, storage, and processing of large and even increasing amounts of information encoded in digital signals. Conversely, methods used in digital signal processing can be exploited to solve particular problems in the design of multiple-valued logic circuits and systems. This paper discusses applicati... View full abstract»

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  • Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals

    Publication Year: 2006, Page(s): 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB) | HTML iconHTML

    Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use... View full abstract»

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