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Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on

Date 17-20 May 2006

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  • 36th International Symposium on Multiple-Valued Logic - Cover

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  • 36th International Symposium on Multiple-Valued Logic - Title

    Page(s): i - iii
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  • 36th International Symposium on Multiple-Valued Logic - Copyright

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  • 36th International Symposium on Multiple-Valued Logic - Table of contents

    Page(s): v - vii
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  • Message from the Symposium Chairs

    Page(s): viii
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  • Message from the Program Chair

    Page(s): ix
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  • Organizing Committee

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  • List of reviewers

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  • Design Methods for Multiple-Valued Input Address Generators

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory. View full abstract»

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  • Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4976 KB) |  | HTML iconHTML  

    This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way. View full abstract»

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  • On Designs of Radix Converters Using Arithmetic Decompositions

    Page(s): 3
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    In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs. View full abstract»

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  • New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design

    Page(s): 4
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    This paper presents an asynchronous encoding scheme using a MVL(Multi-Value Logic). This scheme reduces not only the number of wires but also the switching activities. It is achieved by the two proposed data encoding methods, RT/NRT(Return to Ternary/ Non Return to Ternary) encoding and hybrid ternary one. Conventional ternary encoding makes all data lines to intermediate to generate completion signal. In RT/NRT encoding, however, data lines with transferring zero do not change to intermediate value in order to reduce the switching activities. In hybrid ternary encoding, it needs only two half-swing to transfer 2-bit data. Indeed, it only needs two lines. As the results, a RT/NRT encoding shows 25% reduction in the signal transition and it achieve power reduction about 27% comparing to the conventional ternary one. In addition, a hybrid ternary encoding achieves 23% energy reduction. View full abstract»

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  • Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic

    Page(s): 5
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    A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise reduction. Since a dual-rail complementary duplication is performed by using two differential-pair circuits (DPCs), noise effect is distributed to only one DPC, if common-mode noise is applied to dual-rail input lines. The dual-rail complementary duplicated DPCs makes noise effect reduced, because one of the DPC makes error operation and the other makes no-error operation, so that the output noise level which is summed up of two DPCs becomes half. By using the Schmitt-trigger circuit, the half-level noise effect from two DPCs is almost eliminated. As a typical design example of arithmetic modules, it is discussed to implement a crosstalk-noise-free radix-2 signed-digit full adder in a 0.18ìm CMOS technology at the supply voltage of 1.8V . View full abstract»

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  • Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

    Page(s): 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    This paper presents an evaluation of multiple-valued packet multiplexing scheme for a Network-on-Chip (NoC) architecture. In the NoC architecture, data is transferred from one Processing Element (PE) to another PE through the routers in the form of a packet. A router, suitable for both the binary and the multiple-valued packets, is constructed using the Multiple Valued Source-Coupled Logic circuits. A packet is composed of flag, destination PE address and data fields. In the NoC architecture, packets are generated by microprogram control. In the proposed scheme, two binary packets are multiplexed if the destination PE addresses are the same. Based on address matching, packets are transferred from a source PE to a destination PE autonomously. As a result, the total number of packets can be reduced. The router is designed using 0.18ìm CMOS design rule. HSPICE simulation results show that the delay of the router is significantly small for high speed packet transfer. Reduction of microprogram control storage is remarkable in the proposed scheme, because the data transfer can be done autonomously. The advantage is evaluated by simple analysis, and comparison with a conventional pipelined bus architecture is done. View full abstract»

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  • On the Ranges of Algebraic Functions in Lattices - A Preliminary Report

    Page(s): 7
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    We investigate ranges of ternary algebraic functions in lukasiewicz-Moisil algebras, where we give a characterization of algebraic functions whose ranges are intervals and we retrieve a canonical form of functions over three-element ternary lukasiewicz-Moisil algebras, a result due to Gr. C. Moisil, one of the founders of switching theory [Moi57]. In the second part of this paper we show that in a Noetherian or Artinian lattice distributivity and boundedness are implied by the condition that every algebraic functions has an interval as its range; this is actually a characterization of boundedness and distributivity in the class of lattices that have finite chains. View full abstract»

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  • Upper and Lower Bounds on the Number of Disjunctive Forms

    Page(s): 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    We evaluate the upper and lower bounds on the number of disjunctive (normal) forms of an n-variable Boolean function (for our purpose it is sufficient to take the constant 1 function which always takes the value 1). We use a one-to-one correspondence between the disjunctive forms and the antichains in the ternary n-cube which is isomorphic to the partially ordered set formed by all terms of the given function. For the upper bound we use a newly invented decomposition of the partially ordered set into chains (we introduce trees which span the cube). For the lower bounds, we evaluate the number of anticains in the cube by analyzing the dependency among the three consecutive layers instead of two. Put DF(1) the number of different disjunctive forms for the constant 1 function. We obtain newly improved upper and lower bounds. View full abstract»

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  • Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta

    Page(s): 9
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    All first-order G¨odel logics GV with globalization operator based on truth value sets V C [0,1] where 0 and 1 lie in the perfect kernel ofV are axiomatized by Ciabattoni’s hypersequent calculus HGIF [10]. View full abstract»

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  • Assumption based multi-valued semantics for extended logic programs

    Page(s): 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    The paper presents an approach for handling uncertain information in extended logic programs using multi-valued logics defined by bilattices. Uncertainty means that the atoms may be assigned logical values other than the conventional ones - true and false, in the semantics of the program. The logical values represent various degrees of truth, which may be combined and propagated by applying the program rules. However, as not any atom can be derived through the program rules, the resulting incomplete information problem is treated here by using assumptions, according to which atoms not derivable may be assigned a (default) logical value. Our approach extends the concept of assumption by employing any value from the considered multi-valued logic as a default value. We define the assumption based multi-valued semantics that extends successful conventional logic programming semantics as the well-founded semantics and the Kripke-Kleene semantics. We show that our semantics has a polynomial data complexity. View full abstract»

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  • Implementation of Multiple-Valued CAM Functions by LUT Cascades

    Page(s): 11
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    In this paper, we introduce three types of multiplevalued content-addressable memories (CAMs): ordinary CAMs (CAMs), distance d CAMs, and *CAMs. Ordinary CAMs require an exact match, while *CAMs allow wildcard matches. In a distance d CAM, a match occurs even if at most d digits differ. Then, we define multiple-valued CAM functions represented by these CAMs. Next, we show an approach to realize each CAM function by an LUT cascade, which is a series connection of RAMs. Experimental results for both two-valued and multi-valued cases are shown. View full abstract»

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  • The new architecture of radix-4 Chinese abacus adder

    Page(s): 12
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    In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35µm, 0.25µm, and 0.18µm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35µm, 0.25µm, and 0.18µm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder. View full abstract»

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  • Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit

    Page(s): 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VLSI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)- based threshold logic gate, a dynamic latch and a switch block. The threshold logic gate consists of only one universal comparator. A single DPC is used as a component of the universal comparator. By using programmable current sources for the DPC, the driving capability of the cell and the weight of the output can be changed according to the reconfigured information. The DPC compares a multiplevalued (MV) input with a threshold which is provided by a programmable threshold voltage generator. This leads to the high utilization of the cell because almost all the universal comparators in the VLSI chip can be utilized effectively without idle states. Furthermore, fine-grain pipelining increases the throughput of the VLSI. The VLSI is designed using 0.18ìm CMOS standard design rule. HSPICE simulation results show that, the throughput and the power consumption are greatly improved in comparison with the equivalent VLSI reported until now. View full abstract»

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  • Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits

    Page(s): 14
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    New four-valued logic and static storage components using differential-pair circuits (DPCs) are proposed for a high-performance microprocessor datapath. The DPCbased circuit makes a signal-voltage swing small yet the current-driving capability large, and generates complementary outputs. Both a four-valued comparator and a binary static latch can be merged into a simple DPC-based circuit structure, which achieves low-power dissipation and small chip area while maintaining high-speed switching. As a typical application, a 32-bit microprocessor datapath with five pipelining stages is implemented using the proposed circuit technique in 0.18ìm CMOS, and its advantages are demonstrated in comparison with a corresponding CMOS implementation. View full abstract»

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  • A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors

    Page(s): 15
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    In this work some Multi-Valued Logic (MVL) blocks are initially presented and they will be used to the final building of a Quaternary half-adder. A circuit equivalent to an Exclusive-OR binary gate from the binary world but working for the quaternary world is performed. Also, other basic gates are necessary like the shifter circuit, equivalent to the Not gate of the binary world, and the switching block, a core for the circuits here presented. All the circuits are built with bipolar transistors operating in current-mode. View full abstract»

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  • Signal Processing Algorithms and Multiple-Valued Logic Design Methods

    Page(s): 16
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    Multiple-valued logic can be viewed as an alternative approach to solving many problems in transmission, storage, and processing of large and even increasing amounts of information encoded in digital signals. Conversely, methods used in digital signal processing can be exploited to solve particular problems in the design of multiple-valued logic circuits and systems. This paper discusses applications of group-theoretic methods used in digital signal processing to derivation of compact representations for multiple-valued logic functions and the design of multiplevalued logic circuits with regular structures. View full abstract»

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  • Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals

    Page(s): 17
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    Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one. View full abstract»

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