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Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Date 7-9 Dec. 2004

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Displaying Results 1 - 25 of 163
  • [Front cover]

    Publication Year: 2004 , Page(s): C1
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  • 2004 IEEE International Conference on Semiconductor Electronics (IEEE Cat. No.04EX917C)

    Publication Year: 2004
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  • Copyright page

    Publication Year: 2004 , Page(s): II
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  • Message from Chairman

    Publication Year: 2004 , Page(s): III
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  • Conference committee

    Publication Year: 2004 , Page(s): IV
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  • Table of contents

    Publication Year: 2004 , Page(s): V - XIX
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  • InP/InGaAs heterojunction phototransistors for optoelectronic receivers

    Publication Year: 2004
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1240 KB)  

    A theoretical and experimental analysis of the performance of InP/InGaAs heterostructure phototransistors (HPT) has been carried out and comparisons made with avalanche photodiodes (APDs) and PIN-HBT photodetectors. Although the APDs are intrinsically faster, the HPT in travelling-wave form has demonstrated excellent responsivity and power handling capability. View full abstract»

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  • Colloidal self-organization for nanoelectronics

    Publication Year: 2004
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3608 KB) |  | HTML iconHTML  

    The major part of the expenses in modern IC manufacturing process is nowadays devoted to the R & D needed to optimize chip size, wafer size, defectivity and interconnects- building up to keep Moore's law a reality. But the question is: Can circuits with sub-0.1 μm dimensions be fabricated by the extension of current device production technologies? An interdisciplinary 'off the beaten path' appr... View full abstract»

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  • Modeling and simulation for ESD protection circuit design and optimization

    Publication Year: 2004
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3496 KB) |  | HTML iconHTML  

    An overview of the application of modeling and simulation methodologies for ESD protection circuit design optimization is presented. This methodology will reduce the development cycle time and costs and consists of a device compact model definition valid under ESD conditions and circuit level optimization of the protection circuits. This enables to extract information on the ESD robustness of the ... View full abstract»

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  • Low temperature bonding process for wafer-level MEMS packaging

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4096 KB) |  | HTML iconHTML  

    In this paper, the development of low temperature (less than 300 C) bonding techniques of Si-to-glass, glass-to-glass and Si-to-Si is reported. To improve the bond quality of Si-to-glass and make glass-to-glass bonding viable, an amorphous silicon layer of 20-100 nm thickness is deposited as an intermediate layer. For Si-to-glass bonding, without applying the amorphous film, both the bond efficien... View full abstract»

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  • On-line water quality monitoring on Brantas river East Java Indonesia

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2800 KB) |  | HTML iconHTML  

    Twenty three on-line water quality monitoring stations have been built along Brantas river in East Java. The construction of these online stations has been aimed at providing accurate, real-time, programmed, and continuous data on the quality of the Brantas river water, such that the occurrence of a certain level of water pollution can be detected on time. The placement of these twenty three stati... View full abstract»

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  • Reliability of MSQ spin-on glass as low-k interlayer dielectric in VLSI device

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    There has been increasing trend to reduce the size of VLSI device dimension for speed improvement. However, another trend to improve the speed is to reduce the parasitic RC that exists in a VLSI device. Low-k dielectric thin film acting as interlayer dielectric is used to reduce the parasitic capacitance between metal layers. There are two main types of low-k dielectric based on the deposition met... View full abstract»

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  • Effect of germanium cap layer on indium ohmic contacts for n-type GaAs

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1928 KB) |  | HTML iconHTML  

    Ohmic contacts from Ge/In were successfully fabricated. Thin film of In and Ge were sequentially deposited onto a clean n-type GaAs surface as contact and followed by annealing at various temperatures up to 800 C in nitrogen ambient. Ge acted as a capping layer and promoted formation of InAs. Linear TLM and contact end resistance measurement were employed to characterize the specific contact resis... View full abstract»

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  • Influence of contact dimension on end resistance characterization for transmission line model

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2352 KB) |  | HTML iconHTML  

    The influence of contact dimension and semiconductor sheet resistance on end resistance, RE, was investigated with ISE TCAD simulator. Since it is difficult to accurately measure RE experimentally due to its mathematical definition, potential distributions in the vicinity of the contacts were simulated in order to extract relationship between the apparent and actual R... View full abstract»

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  • Modeling of diaphragms for micromachined condenser microphones

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2768 KB) |  | HTML iconHTML  

    We present and compare the different kinds of diaphragms for micromachined condenser microphones. The aim is to develop the microphones with high sensitivity. For micromachining diaphragm, there is significant internal (residual) stress, which strongly decreases the mechanical sensitivity of diaphragm. An analysis was performed using the MATLAB software. According to our calculations, a corrugated... View full abstract»

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  • Condenser microphone performance simulation using equivalent circuit method

    Publication Year: 2004
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3456 KB) |  | HTML iconHTML  

    This paper presents the analysis of a condenser microphone for use in a hearing instrument and proposes a structure that can be realized using microelectromechanical systems (MEMS) technology. The microphone uses a thin low stress polysilicon with an air gap and a silicon nitride perforated back plate. The aim is to develop the microphones with high sensitivity and low fabrication cost. The equiva... View full abstract»

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  • A new and effective method in failure analysis of gate oxide polysilicon capacitor structure

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3456 KB) |  | HTML iconHTML  

    In wafer fabrication, gate oxide integrity (GOI) plays an important role in the reliability and yield of integrated circuits. Failure in gate oxide polysilicon capacitor during reliability test and product manufacturing testing is a concern and needs failure analysis to determine the root cause of the failure. The most common method to perform fault isolation is using emission microscope to detect... View full abstract»

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  • Advanced low temperature bonding technologies

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1968 KB) |  | HTML iconHTML  

    The different fields and especially its various applications for microelectromechanical systems (MEMS) prevent the use of uniform packaging techniques for all types of μ-device. Several bonding techniques performed at wafer-scale, with the advantage of protecting the device against particles, contaminations or even damage during the sawing and dicing process are used right now. Most of these te... View full abstract»

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  • A study of changes in oxide properties on metal-oxide-semiconductor (MOS) structure after electrical overstress

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2000 KB) |  | HTML iconHTML  

    In this research, the impact of electrical overstress on the oxide properties of MOS structure is studied. Prior to electrical overstress, normal C-V characteristic is observed and current conduction through the oxide layer is almost negligible. Once the device is subjected to electrical overstress, capacitance no longer depends on voltage, while leakage current increases drastically and is able t... View full abstract»

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  • Performance enhancement of VHDL-AMS for DSP design

    Publication Year: 2004
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1552 KB) |  | HTML iconHTML  

    The behavioural modelling of VHDL-AMS is a key factor in the development of analog and mixed-signal designs for communication devices. This paper presents a framework for the development of programmable mixed-signal devices, which integrates both programmable analog and digital circuits. The framework uses a VHDL-AMS based language, called VHDL-AMS-RTS, to describe the real-time domain and stochas... View full abstract»

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  • Characterization of indium and nitrogen co-implant of NMOSFET for advanced DRAM technologies with dual-gate oxide

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2136 KB) |  | HTML iconHTML  

    Indium and nitrogen implant were used to form the NMOSFET retrograde channel and low-threshold thin-oxide devices respectively. These two impurities are implanted into the same channel before gate oxidation for an advanced sub-0.12μm DRAM technology. In this paper, the impacts of nitrogen and indium implant on the current-voltage, Qbd of the ultra-thin gate oxides and hot carrier lifetime of th... View full abstract»

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  • Hydrogen sensitive Pt Schottky diode sensor based on GaN

    Publication Year: 2004
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1280 KB) |  | HTML iconHTML  

    Pt/GaN devices operated as Schottky diodes were characterized for their hydrogen gas sensitivity. The sensors are tested at different concentrations of hydrogen gas as a function of operating temperature. The Pt thin film (100nm) was prepared and deposited by sputtering method. The electrical characterization was made using (I-V) current voltage of the temperatures range of 25 C to 500 C. Result s... View full abstract»

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  • Delay macro modeling of CMOS gates using modified logical effort technique

    Publication Year: 2004
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1400 KB) |  | HTML iconHTML  

    Modified logical effort (MLE) technique is proposed in this paper to provide delay estimation for CMOS gates. The model accounts for the behavior of series connected MOSFET structure (SCMS), the switching input transition time and internodal charges. Also the model takes into account deep submicron effects such as mobility degradation and velocity saturation. This model exhibits a good accuracy wh... View full abstract»

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  • An automated tool deployment for ESD (electrostatic-discharge) correct-by-construction strategy in 90 nm process

    Publication Year: 2004
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3136 KB) |  | HTML iconHTML  

    Continuous device scaling adhering to Moore's law imposes a greater challenge to the product design envelop. The complexity of ESD protection design can be enormous due to high degree of integration, including high signal count and mix-signal considerations. It is likely to take several design iterations before the specified ESD requirements can be guaranteed (Dabral and Maloney, 1998; Amerasekera... View full abstract»

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  • A high-speed direct bootstrapped CMOS Schmitt trigger circuit

    Publication Year: 2004
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (504 KB)  

    This paper proposes a design of direct bootstrapped CMOS Schmitt trigger circuit by using direct bootstrapped technique, bootstrapped capacitor boots for the higher voltage than power supply in order to drive the output section for improving the switching speed in driving a capacitive load. All simulation results have been carried out based on PSpice program simulator by using 0.35 μm CMOS tech... View full abstract»

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