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Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Date 7-9 Dec. 2004

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  • [Front cover]

    Page(s): C1
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  • 2004 IEEE International Conference on Semiconductor Electronics (IEEE Cat. No.04EX917C)

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  • Copyright page

    Page(s): II
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  • Message from Chairman

    Page(s): III
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  • Conference committee

    Page(s): IV
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  • Table of contents

    Page(s): V - XIX
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  • InP/InGaAs heterojunction phototransistors for optoelectronic receivers

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    A theoretical and experimental analysis of the performance of InP/InGaAs heterostructure phototransistors (HPT) has been carried out and comparisons made with avalanche photodiodes (APDs) and PIN-HBT photodetectors. Although the APDs are intrinsically faster, the HPT in travelling-wave form has demonstrated excellent responsivity and power handling capability. View full abstract»

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  • Colloidal self-organization for nanoelectronics

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    The major part of the expenses in modern IC manufacturing process is nowadays devoted to the R & D needed to optimize chip size, wafer size, defectivity and interconnects- building up to keep Moore's law a reality. But the question is: Can circuits with sub-0.1 μm dimensions be fabricated by the extension of current device production technologies? An interdisciplinary 'off the beaten path' approach is mandatory to overcome future limitations. One such approach is fabrication of devices (or at least parts of devices) by self-organization. View full abstract»

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  • Modeling and simulation for ESD protection circuit design and optimization

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    An overview of the application of modeling and simulation methodologies for ESD protection circuit design optimization is presented. This methodology will reduce the development cycle time and costs and consists of a device compact model definition valid under ESD conditions and circuit level optimization of the protection circuits. This enables to extract information on the ESD robustness of the product at pre-silicon phase and could lead to first-time-right product designs. View full abstract»

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  • Low temperature bonding process for wafer-level MEMS packaging

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    In this paper, the development of low temperature (less than 300 C) bonding techniques of Si-to-glass, glass-to-glass and Si-to-Si is reported. To improve the bond quality of Si-to-glass and make glass-to-glass bonding viable, an amorphous silicon layer of 20-100 nm thickness is deposited as an intermediate layer. For Si-to-glass bonding, without applying the amorphous film, both the bond efficiency and bond strength are low. With the assistance of the amorphous film, the bond quality is significantly improved. Glass-to-glass bonding has also been successfully achieved at low temperature with the amorphous film as intermediate layer. Direct Si-to-Si bonding can be realized at a bonding temperature of 400 C with high bond strength and bond efficiency. Using a sol-gel intermediate layer, the bonding temperature can be reduced to less than 300 C. High bond strength is still maintained, while the bond efficiency is becoming a concern. The bonding mechanisms are proposed. View full abstract»

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  • On-line water quality monitoring on Brantas river East Java Indonesia

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    Twenty three on-line water quality monitoring stations have been built along Brantas river in East Java. The construction of these online stations has been aimed at providing accurate, real-time, programmed, and continuous data on the quality of the Brantas river water, such that the occurrence of a certain level of water pollution can be detected on time. The placement of these twenty three stations, as well as the types of parameters detected by the sensors inside the stations, has been based on the characteristics of the river water at each location. With this, the source of water pollution can be detected more accurately. The measured parameters include pH, temperature, conductivity, dissolved oxygen, turbidity, orthophosphate, and ammonia. The ability and effectiveness of these on-line stations in detecting water pollution in the Brantas river will be printed in this paper. View full abstract»

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  • Reliability of MSQ spin-on glass as low-k interlayer dielectric in VLSI device

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    There has been increasing trend to reduce the size of VLSI device dimension for speed improvement. However, another trend to improve the speed is to reduce the parasitic RC that exists in a VLSI device. Low-k dielectric thin film acting as interlayer dielectric is used to reduce the parasitic capacitance between metal layers. There are two main types of low-k dielectric based on the deposition method; i.e. spin-on and chemical vapor deposition. In this paper, the reliability problem due to metal diffusion of spin-on glass type low-k dielectric called methylsilsesquioxane (MSQ) is discussed. The results also showed that the method of metal deposition does affect the diffusion through the MSQ layer due to differences in thermal energy for each deposition method and therefore affecting the reliability of this thin film to act as a dielectric. View full abstract»

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  • Effect of germanium cap layer on indium ohmic contacts for n-type GaAs

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    Ohmic contacts from Ge/In were successfully fabricated. Thin film of In and Ge were sequentially deposited onto a clean n-type GaAs surface as contact and followed by annealing at various temperatures up to 800 C in nitrogen ambient. Ge acted as a capping layer and promoted formation of InAs. Linear TLM and contact end resistance measurement were employed to characterize the specific contact resistance, ρc. Lowest ρc obtained with Ge/In contact was 3.38 10-3 Ωcm2. Due to unintentional oxidation reduction in specific contact resistance by Ge was not observed. View full abstract»

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  • Influence of contact dimension on end resistance characterization for transmission line model

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    The influence of contact dimension and semiconductor sheet resistance on end resistance, RE, was investigated with ISE TCAD simulator. Since it is difficult to accurately measure RE experimentally due to its mathematical definition, potential distributions in the vicinity of the contacts were simulated in order to extract relationship between the apparent and actual RE value. The simulation was built on circular and linear transmission line model (TLM) structures. It was found that apparent RE obtained through measurement was lower than its actual value in large width contacts (down to 0.1% of actual RE) and also in those deposited on thin semiconductor substrate. This trend was also found in semiconductor substrate with smaller modified sheet resistance. The results presented here can serve as a guideline to design TLM structures with less deviated value of apparent RE when end resistance characterization is necessary. View full abstract»

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  • Modeling of diaphragms for micromachined condenser microphones

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    We present and compare the different kinds of diaphragms for micromachined condenser microphones. The aim is to develop the microphones with high sensitivity. For micromachining diaphragm, there is significant internal (residual) stress, which strongly decreases the mechanical sensitivity of diaphragm. An analysis was performed using the MATLAB software. According to our calculations, a corrugated diaphragm can greatly increase the mechanical sensitivity of the microphone diaphragms due to the reduction of the initial stress effect without changing the process conditions. A planar diaphragm is more rigid than a corrugated diaphragm at either small and large deflections (or pressures) when both diaphragms have same level of initial stress. Flat diaphragms show a nonlinear relation between the deflection and the applied pressure. The nonlinearity is caused by stress due to stretching of the diaphragm. It has been shown that corrugated diaphragms have a larger linear range than flat diaphragms, because of the achieved reduction of the initial stress in the diaphragm. View full abstract»

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  • Condenser microphone performance simulation using equivalent circuit method

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    This paper presents the analysis of a condenser microphone for use in a hearing instrument and proposes a structure that can be realized using microelectromechanical systems (MEMS) technology. The microphone uses a thin low stress polysilicon with an air gap and a silicon nitride perforated back plate. The aim is to develop the microphones with high sensitivity and low fabrication cost. The equivalent circuit method has been used to evaluate the performance of the microphone. The microphone diaphragm has a proposed thickness of 0.8 μm, an area of 2.6 mm2, an air gap of 3.0 μm and a 1.0 μm thick back plate with acoustical ports. A 12.0 volt DC bias voltage is provided between the diaphragm and the back plate. A sensitivity of more than 45.0 mV/Pa is expected for the microphone, with a high frequency response extending to 20 kHz. View full abstract»

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  • A new and effective method in failure analysis of gate oxide polysilicon capacitor structure

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    In wafer fabrication, gate oxide integrity (GOI) plays an important role in the reliability and yield of integrated circuits. Failure in gate oxide polysilicon capacitor during reliability test and product manufacturing testing is a concern and needs failure analysis to determine the root cause of the failure. The most common method to perform fault isolation is using emission microscope to detect the emission spot. The challenging area to identify the defect in gate oxide polysilicon capacitor is the difficulty in removing bulk polysilicon of the structure. Although polysilicon etchant and acetone tape are used extensively, it always does not guarantee to successfully remove the polysilicon and most of time the success rate is low time consuming as it requires long time to delayer the structure. Thus in this paper a method was developed and bulk polysilicon can be etched in few seconds and the whole process of deprocessing can be completed in few minutes, greatly enhance the efficiency of performing failure analysis and resolves the difficulty encountered in Chartered. This method consists of dipping sample in SCI solution (1NH4OH:1H2O2:5H2O) follows by polysilicon etch (20HNO3:8CH3COOH:1HF). View full abstract»

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  • Advanced low temperature bonding technologies

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    The different fields and especially its various applications for microelectromechanical systems (MEMS) prevent the use of uniform packaging techniques for all types of μ-device. Several bonding techniques performed at wafer-scale, with the advantage of protecting the device against particles, contaminations or even damage during the sawing and dicing process are used right now. Most of these techniques are performed at high temperatures during the bond, wet cleaning process steps - totally inapplicable for μ-moving parts - or insufficient hermeticity in the final package. Bonding techniques based on dry plasma activation and adhesive wafer-level bonding of MEMS are therefore a very interesting alternative to the common techniques. Main advantages of these two techniques are: temperature sensitive devices or heterogeneous materials with different CTE can be bonded together on wafer scale; there is no wet activation or cleaning processes involved. View full abstract»

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  • A study of changes in oxide properties on metal-oxide-semiconductor (MOS) structure after electrical overstress

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    In this research, the impact of electrical overstress on the oxide properties of MOS structure is studied. Prior to electrical overstress, normal C-V characteristic is observed and current conduction through the oxide layer is almost negligible. Once the device is subjected to electrical overstress, capacitance no longer depends on voltage, while leakage current increases drastically and is able to be detected by a photon emission microscope. Physical defects such as oxide damage and pinholes could be observed under a variable pressure field emission scanning electron microscope. These defects are highly likely induced during fabrication process and detrimental to the oxide strength. View full abstract»

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  • Performance enhancement of VHDL-AMS for DSP design

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    The behavioural modelling of VHDL-AMS is a key factor in the development of analog and mixed-signal designs for communication devices. This paper presents a framework for the development of programmable mixed-signal devices, which integrates both programmable analog and digital circuits. The framework uses a VHDL-AMS based language, called VHDL-AMS-RTS, to describe the real-time domain and stochastic behaviour to adapt the simulation and performance analysis. The real-time stochastic statements of VHDL-AMS-RTS are added to the VHDL-AMS, which include time ordering and time constraint, probabilistic behaviour and quantitative description of mixed-signal devices. With this behavioural modelling environment it is possible to predict and optimize the analog and digital hardware using simulation but with a lower computational time and cost. To demonstrate the usefulness of the framework, we apply it to the structural performance analysis of soft input soft output (SISO) module of turbo decoding. View full abstract»

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  • Characterization of indium and nitrogen co-implant of NMOSFET for advanced DRAM technologies with dual-gate oxide

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    Indium and nitrogen implant were used to form the NMOSFET retrograde channel and low-threshold thin-oxide devices respectively. These two impurities are implanted into the same channel before gate oxidation for an advanced sub-0.12μm DRAM technology. In this paper, the impacts of nitrogen and indium implant on the current-voltage, Qbd of the ultra-thin gate oxides and hot carrier lifetime of the NMOSFET were investigated. It was found that high dose of the indium implant degrades the oxide integrity. Furthermore, enhanced GOI degradation, such as increasing ratio of the A-mode oxide breakdown was observed for the nitrogen and indium co-implantation. However, based on our investigation, TDDB of gate oxides and hot-carrier lifetime of NMOSFET can reach lifetime criteria for a current 0.12μm trench DRAM technology if proper process conditions are selected. View full abstract»

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  • Hydrogen sensitive Pt Schottky diode sensor based on GaN

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    Pt/GaN devices operated as Schottky diodes were characterized for their hydrogen gas sensitivity. The sensors are tested at different concentrations of hydrogen gas as a function of operating temperature. The Pt thin film (100nm) was prepared and deposited by sputtering method. The electrical characterization was made using (I-V) current voltage of the temperatures range of 25 C to 500 C. Result shows the current output increased as operating temperature increases and decreased as temperature exceed 200 C. The maximum sensor sensitivity recorded in terms of current detected showed higher value than those obtained form Pt/Si and Pt/SiC sensor diode at similar temperature. Sensitivity also increases as the concentration of H2 gas increased. Further more, the sensor shows remarkable sensitivity stability and retained it at broad temperature range of 25 C up to 200 C. View full abstract»

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  • Delay macro modeling of CMOS gates using modified logical effort technique

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    Modified logical effort (MLE) technique is proposed in this paper to provide delay estimation for CMOS gates. The model accounts for the behavior of series connected MOSFET structure (SCMS), the switching input transition time and internodal charges. Also the model takes into account deep submicron effects such as mobility degradation and velocity saturation. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model. An average error of 3.1% was obtained based on UMC's 0.13μm technology. View full abstract»

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  • An automated tool deployment for ESD (electrostatic-discharge) correct-by-construction strategy in 90 nm process

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    Continuous device scaling adhering to Moore's law imposes a greater challenge to the product design envelop. The complexity of ESD protection design can be enormous due to high degree of integration, including high signal count and mix-signal considerations. It is likely to take several design iterations before the specified ESD requirements can be guaranteed (Dabral and Maloney, 1998; Amerasekera and Duvvury, 1995). In view of a shorter design cycle coupled with overwhelming technological challenges in the leading edge 90nm process, an automated tool (RVCAT-ESD) has been deployed for the verification of ESD design rules during the product development stage. The tool can effectively verify both local and global ESD protection rules on the design database. The tool is also capable of providing a panoramic view of the ESD violation nodes in the design layout using the "overlay" feature. This helps to efficiently pin-point ESD design weaknesses in the design layout, such as current congestion, insufficient metal width and etc. This allows ESD design rules compliance in the early design stage, thus enhancing the approach of "correct-by-construction" on ESD design. View full abstract»

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  • A high-speed direct bootstrapped CMOS Schmitt trigger circuit

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    This paper proposes a design of direct bootstrapped CMOS Schmitt trigger circuit by using direct bootstrapped technique, bootstrapped capacitor boots for the higher voltage than power supply in order to drive the output section for improving the switching speed in driving a capacitive load. All simulation results have been carried out based on PSpice program simulator by using 0.35 μm CMOS technology with level 3. The propagation delay time of the proposed circuit becomes less at 2.186 ns, low power dissipation and gives a full swing output voltage at 1 voltage supply and also operates at 100 MHz, it is higher 10 times as a previous result when compared with the conventional CMOS Schmitt trigger circuit and reshaping CMOS Schmitt trigger circuit. View full abstract»

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