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Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th

Date 7-9 Dec. 2005

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  • [Cover]

    Page(s): C1
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  • [Title page]

    Page(s): i
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  • Copyright page

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  • Foreword

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  • Conference committee

    Page(s): iv - v
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  • Table of contents

    Page(s): vi - xviii
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  • Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection

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    3D packaging (3DP) is an emerging trend as a solution for microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of multistack flip chip 3D packaging with TSVs for interconnection is designed and fabricated. Processing techniques for prototype fabrication are studied and discussed in details. The formation of TSVs is by the deep reactive ion etching (DRIE) process and the plugging of TSVs is by copper plating. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this paper View full abstract»

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  • Direct metal to metal bonding for microsystems interconnections and integration

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    In microsystems integration, microsystem devices with different functions are needed to be electrically connected. To meet higher component needs, more functions are configured within each device which leads to a significant potential in microsystems integration, industrial interests have grown exponentially in search of complementing integration and low temperature direct interconnection bonding technology to bridge this bottleneck. This area is especially profound in flip-chip thermocompression technology and chip design for high-density interconnection, since conventional soldering process may not be able to address the generic limitation of relatively high process temperature, solder bump geometry, under-bump-metallization (UBM) schemes and intermetallic effects. This underlying problem necessitates a low temperature direct metal bonding technique for joining multifunctional microsystems which offers more reliable and higher density interconnections than soldering and the wire bonding techniques. In this paper, Au-Au bonding was identified as potential technique to integrate microsystems. Bonding parameters and bond quality were deliberated in multifactorial experiments to determine optimum loading and temperature. Bonding mechanisms and reliability were established with tensile and shear test evaluation. The results show that Au-Au bonding can be achieved at temperatures only above a threshold value. Results for Au-Au bonding exhibit a critical temperature beyond which no bonding can take place. Above the critical temperature, tensile strength of the Au-Au joint reaches a maximum with increase in bonding pressure View full abstract»

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  • Error proof inkless die bonding process development

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    Wafer mapping techniques originated at the wafer fab for wafer manufacturing process control and yield improvement as presented by T. Takeda (1994). Recently, inkless assembly processes have been becoming more and more popular for wafer fab process simplification and cycle time reduction, as well as the graded IC product sale under the pressure of IC manufacturing cost. However, not all of the packaging and assembly houses are ready for wafer mapping, as converting from the current inked wafer process to inkless assembly includes a lot of challenges to assembly equipment, process and manufacturing control, especially for smaller die sizes (less than 1times1mm). This paper discusses the critical challenges of handling inkless wafers to packaging and assembly. Technical solutions are developed including error-proof inkless packaging process flow, reference die design, inkless die pick up arithmetic, and pattern recognition optimization. The scenarios of fatal impact to inkless wafer mapping implementation are captured and solutions are provided that guarantee smooth implementation of inkless assembly View full abstract»

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  • Reliability of Cu/low-k wafer level package (WLP)

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    With the move to 300 mm wafer, WLP becomes even more attractive as the solution for backend processing. More importantly as an enabling technology for the most advanced 0.13 micron technology using Cu/low-k interconnect devices. Cu/low-k devices need WLP since wire-bond forces could damage the soft device structures. Additionally, low-k interconnect densities often reach values that can only be accommodated by area-array packaging technology. Low-k materials are mechanically, chemically, thermally, and electrically less stable than the historical material of choice, SiO2. Therefore, the challenge lies not only in identifying and characterizing the candidate materials, but also in devising the best method to integrate those materials for packaging. Test wafer was fabricated with 4 Cu/low-k (black diamond) dielectrics layers. And it has multilayer via-chain to check the internal ILD stack reliability. Die size was 15mm times 15mm and IO no. was about 800. Using these test wafers, WLP was fabricated with multidielectrics layers (BCB) and Cu metal redistribution. Wafer level package has 300 mum pitch solder bump and Cu post interconnects to get better board level solder joint reliability. Cu post and solder cap were prepared by electroplating method. To investigate the solder joint integrity, daisy chains are connected to the PCB board and resistance was electrically monitored. Board level solder joint reliability is performed in temperature cycle chamber (-45/120C) View full abstract»

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  • Simulation methodologies for electromagnetic compatibility (EMC) and signal integrity (SI) for system design

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    Current technology trends require the utilisation of very high clock rates which have a broad electromagnetic spectrum. Electronic equipment designers require accurate characterisation and optimisation of electrical components, sub-systems and complete systems at frequencies that extend well into the microwave spectrum. This paper aims to assess the state-of-the-art in full field solvers in system and sub-system design and in doing so identify the trends in simulation techniques that are targeted towards the development of complex designs which operate at high speeds. Particular emphasis is placed on the treatment of multiscale problems, the development of macronodes containing sub-wavelength features and optimal meshing techniques. Developments in these areas are illustrated with results typical of EMC and SI design issues View full abstract»

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  • Radiation from arbitrary shape power/ground plane pair structure

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    The radiation from power/ground pair structures in high speed printed circuits boards, packages due to the switching noise current has attracted much attention recently. Analytical cavity-resonator model has been proposed for investigation of rectangular power/ground plane pair; however it can not be employed for arbitrary shape power/ground plane pair structure because no analytical solution of the resonating mode is available. The transmission line method is proposed in this paper to analyze the radiation from an arbitrary shaped power/ground plane pair structure View full abstract»

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  • Electromagnetic susceptibility analysis of high speed circuit inside the shielding enclosure with an aperture

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    This paper investigates electromagnetic suspectibility characteristics of high speed circuit inside the shielded enclosure with an aperture. Full wave analysis combined with circuit based method is proposed in order to exploit the advantages of these two techniques. The mixed potential electric field integral equation technique via the method of moment (MoM) is adapted to analyze the external part of the problem domain (enclosures and external signal cables) which is illuminated by plane wave EMI. Circuit based SPICE model is used to analyze the suspectibility characteristics of enclosed high speed circuits View full abstract»

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  • A model for efficient and improved measurements of the complex permittivity of thin organic packaging materials using open-ended coaxial line technique

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    In this paper, the open-ended coaxial line is analyzed and an improved lumped equivalent model proposed. The interaction between the probe, material under test (MUT) and the backing of the MUT is studied and the sample backing was found to have a strong effect over the results, especially over high frequencies. Consequently, an optimum dielectric backing was used for accurate extraction of the complex permittivity of thin packaging materials. The validity of the model was verified through numerical modeling and high frequency measurements, with a good correlation obtained. In particular, the implications of probe polishing on achieving measurement repeatability using the open-ended coaxial line technique were also extensively investigated. Furthermore, the effects of imposing different testing conditions on the dielectric properties of FR4 and Teflon-based laminates were investigated over broadband using the improved model, with the results compared and reported in this paper View full abstract»

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  • Investigation of IMC layer effect on PBGA solder joint thermal fatigue reliability

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    Thermal cycling reliability test and analysis for PBGA with Sn-3.8Ag-0.7Cu lead free solder joints with Ni/Au surface finish were investigated. Failure mode of PBGA component exhibits solders fatigue failure with failure site close to solder/IMC interface. The MTTF was determined by Weibull model and used to calibrate the finite element analysis (FEA) results. Intermetallic compound (IMC) layers of CuNiSn are formed when SnAgCu solder is reflowed on PCB board with Ni/Au finish. The reliability of electronic assembly is affected by IMC during thermal cycling. In this paper, finite element analysis of solder joint reliability has been developed to model the effect of IMC layer on solder joint fatigue behavior. It is shown that the IMC layer reduces the solder joint fatigue life. In this study, the elastic modulus for CuNiSn IMC was measured by nanoindentation using a continuous stiffness measurement technique. The IMC elastic modulus effect on solder fatigue was also investigated by FEA modeling View full abstract»

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  • Improved slim sector model for analysis of solder joint reliability

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    Within the next three years, it is likely that the interconnection pitch of the advanced flip chip will come down to 100 micron. In order to study the solder joint reliability more efficiently, a slim sector model has been developed to handle the large number of interconnects involved (Zhao and Tay, 2003). The number of nodes and elements of the slim sector model is much lesser than that of the traditional one-eighth model. However, more effort, are required in the preprocessing. This paper presents an improved slim sector model. The intermediate layer between chip and substrate is treated as a continuum layer since the solder joints are distributed evenly. The advantage of transversely isotropic behaviour is taken into account. The effective mechanical properties of the equivalent continuum layer are evaluated using a 3D representative volume element (RVE) based on continuum mechanics and a numerical homogenization method. Formulae to extract the effective material constants are derived using elasticity theory. With finite element analysis of four cases of loading to the RVE, transversely isotropic plasticity model are obtained. Characteristic parameters for Hill's formulation are extracted from the numerical experiments. Temperature dependent mechanical properties are taken into account. Thermal reliability analysis of a 6times6mm2 flip chip package was carried out using the continuum layer with effective mechanical properties and heterogeneous structure. Numerical results show that the difference of displacement is 3~5%. As a result, the error percentage of maximum inelastic shear strain and fatigue life prediction is 5% and 9%, respectively. The improvement of time efficiency in terms of preprocessing and computational time is significant View full abstract»

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  • Solder joint fatigue in a surface-mount assembly subjected to mechanical loading

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    A mechanical approach employing cyclic twisting deformation to a surface mount assembly is examined as an alternative to temperature cycling for evaluating solder joints fatigue performance. This highly accelerated test is aimed at reducing solder joint reliability testing cycle time. In this study, the mechanics of solder joints in a surface mount assembly subjected to cyclic twisting deformation on the PCB is investigated. For this purpose, a test package with 24 by 24 peripheral-array solder joints is modeled using the finite element method. Unified inelastic strain theory defines the strain-rate-dependent plastic stress-strain response of the 60Sn-40Pb solder. Cyclic twisting deformation in the range of plusmn1deg at a rate of 120 seconds per cycle was applied to the PCB assembly sub-model. The calculated stress and strain distributions in the critical solder joint are compared with those predicted for temperature cycling and accelerated temperature cycling tests. Results showed that the accumulated inelastic strain concentrates in a small region of the critical solder joint near the component side for temperature cycling and near the pad side for cyclic twisting cycles. The rate of inelastic strain accumulation per fatigue cycle in the solder joint for both thermal cycling (TC1) and mechanical twisting (MT1) tests are similar. Thus mechanical twisting test imparts similar characteristics in terms of the shear strain range to temperature cycling tests. Low cycle fatigue is dominated by localized shear effect as reflected in the largest shear strain range of the hysteresis loops. The Coffin-Manson strain-based model yielded more conservative prediction of fatigue lives of solder joints when compared to energy-based approach View full abstract»

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  • Simulation-based design optimization of solder joint reliability of wafer level copper column interconnects

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    This paper describes a study of solder joint reliability of a copper column (CuC) interconnect scheme in wafer level packages using a simulation-based design optimization methodology to investigate the effects of various design parameters on the solder joint thermo-mechanical reliability and to find the optimal parameter settings. Design of experiments (DoE), surrogate modeling and numerical optimization techniques, together with computer simulation have been integrated in this approach. Four design parameters are involved in this study, namely the chip thickness, substrate thickness, substrate CTE, and CuC height. A full factorial DoE method is adopted to prescribe the required simulation runs. The incremental equivalent plastic strain will serve as the indicator of solder joint thermo-mechanical reliability. By applying this simulation-based design optimization approach, the effects of various parameters are identified and an optimal parameter selling is determined View full abstract»

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  • Impact of drop-in lead free solders on microelectronics packaging

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    Lead-free solders and soldering technology will be a revisited concern in microelectronics packaging challenges to meet the demands of wafers-level packaging and 3D packaging operations where greater demands will be made on soldering smaller pads sizes and the high expectations of solder joint strength and long-term reliability. This paper reports on the drop-in lead-free solder approach and will provide characterization research results on Sn-Ag-Cu-In drop-in solder material composition, wetting and assembly characteristics and mechanics properties for stress-strain and creep performance compared to Sn3.8Ag0.7Cu solder View full abstract»

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  • Stress effect on growth of IMCs at interfaces between Sn-Ag-Cu lead free solder and Cu substrate

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    Excessive intermetallic growth in solder joints would lead to the premature failure and stress is known to influence growth of IMC. However, no existing method is available to study effect of stress on the IMC growth in a controlled manner. In this research, a novel C-ring technique was used to carry out study of the stress effect on IMC growth at the interface between 95.8Sn-3.5Ag-0.7Cu lead-free solder and Cu substrate in three different surface finishing conditions. The growth of IMC was found to be faster in the interface subjected to compressive stress than that subjected to tensile stress for both bare Cu substrate and Cu substrate coated with electroless Ni/Pd plating and immersion Au. However, the applied stress state did not show noticeable difference in IMC growth for the Cu substrate coated with immersion Sn View full abstract»

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  • Fabrication process for high-density wiring interposer using photosensitive multiblock copolyimide insulation layers for 3D packaging

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    We have developed a high-density wiring interposer for 10 Gbps signal propagation using a photosensitive polyimide. We optimized the basic properties of the photosensitive polyimide film and the lift-off process for the metal layer using an image-reversal-patterned negative photoresist for the fabrication of the interposer. We experimentally confirmed that the high-density wiring interposer could be fabricated using the polyimide and gold multilayered structure. Fine metal wiring was smoothly covered by the polyimide, as confirmed by scanning electron microscopy (SEM) of the cross section of the fabricated balance pair strip line structure View full abstract»

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  • Solder joint integrity of various surface finished build-up flip chip packages by 4-point monotonic bending test

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    Board level solder joint integrity was evaluated using the 4-point monotonic bending test. Ball grid array (BGA) pad surfaces of electroless nickel immersion gold (ENIG) and solder over copper (SOC) in combination with solder compositions of eutectic SnPb (63SnPb), Cu-doped solder (63SnPb0.25Cu), and Pb-free solder (Sn3Ag0.5Cu) were tested on circuit boards with OSP pad surface finish to evaluate the solder joint integrity at the time of board mounting. The interface and intermetallic compound (IMC) layers were analyzed with SEM and EDX. Test results indicated that BGA solder joints had higher fracture strength when assembled onto a SOC package substrate surface finish than when fabricated on an ENIG surface finish. For solder balls attached to an ENIG plated substrate, fracture strength increased and brittle fracture rate decreased when a solder which includes Cu was used. Failure analysis indicated that for ENIG samples, SnPb eutectic has less remaining IMC at the Ni layer surface and a thicker phosphorus rich (P-rich) layer than either Pb-free or Cu-doped solder. The combination of surface finish and solder type affects not only the IMC/P-rich layer formation, but the fracture strength and failure mode as well View full abstract»

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  • Polymer based optical interconnect module for a bidirectional transceiver and optical N/spl times/M star couplers for datacom applications with data rates > 1Gbps

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    Optical data communication will play an important role in future high speed data links. Especially in datacom applications data rates in Gbps area will be desired. An overall low cost approach is needed on both sides, for the opto-electronic integration and for the passive optical interconnects. Opto-electronic integration will be reached through the use of one- or bidirectional transceivers for datacom based - in future - on surface emitting lasers (VCSEL), instead of LEDs used today, and economically favourable silicon detectors. This additionally requires passive optical interconnects using beam shaped low-cost microoptical components such as, microlenses for in- and out-coupling which are more and more popular in recently developed opto-electronical devices. Ideally, microoptical components can be integrated in passive optical interconnects and replicated in polymer materials for the cost reducing. Hence, the increase of data rate depends on the quality of the optical surfaces. In this paper the manufacturing technologies for fabrication of optical surfaces are discussed. Furthermore, polymer based components are presented which can be used for coupling and routing of optical signals, e.g. a passive optical interconnect for the passive coupling into photodiode or from VCSEL and optical NtimesM star couplers. The polymer based interconnect module has been realized in different polymers (polymethyl methacrylate, PMMA, and cycloolefin copolymer, COC). Total loses and data rates achieved are 3.3 dB and 2 Gbps, respectively. Average total loss an e.g. polymer based 16times16 optical star coupler is better than 17 dB per channel with a uniformity of 3 dB. For replication of polymer substrates of these components hot embossing tools have been produced by combination of deep lithography, ultra-precise milling and micromachining View full abstract»

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  • Manufacture of two-dimensional monomode optical fiber array using MEMS technology

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    A method to manufacture 2D bundles of optical single mode fibres has been developed and demonstrated. The method is based on actively aligning metal coated fibres using electrostatic forces. We report the analytical modelling and simulation of the system using FEMLABreg View full abstract»

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  • Fabrication of low-cost panel sized optical-printed circuit boards

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    Integration of optical interconnects into printed circuit boards are seen as a promising solution to overcome challenges encountered with high frequency electrical interconnects. In this paper, we show some of the results obtained with development of high-speed 10-Gb/s parallel optical interconnects embedded on printed circuit boards. Multimode polymer waveguides are fabricated with commercially available optical materials. Low-cost volume processes are evaluated and utilized for optical-PCB fabrication. Different optical passive components are characterized for point-to-point and point-to-multipoint connections. Additionally, different optical I/O-coupling schemes in the waveguide-emitter/detector device interface are presented and evaluated in terms of cost and complexity. Some critical issues in optoelectronic device assembly and board fabrication are addressed View full abstract»

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