Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Advanced Thermal Processing of Semiconductors, 2005. RTP 2005. 13th IEEE International Conference on

Date 4-7 Oct. 2005

Filter Results

Displaying Results 1 - 25 of 65
  • [Cover]

    Publication Year: 2005 , Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (255 KB)  
    Freely Available from IEEE
  • 13/sup th/ IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005 , Page(s): nil2
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005 , Page(s): nil2
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • Copyright page

    Publication Year: 2005 , Page(s): nil3
    Save to Project icon | Request Permissions | PDF file iconPDF (53 KB)  
    Freely Available from IEEE
  • Conference committee

    Publication Year: 2005 , Page(s): nil4
    Save to Project icon | Request Permissions | PDF file iconPDF (44 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2005 , Page(s): nil5 - nil10
    Save to Project icon | Request Permissions | PDF file iconPDF (443 KB)  
    Freely Available from IEEE
  • Information for authors

    Publication Year: 2005 , Page(s): nil11
    Save to Project icon | Request Permissions | PDF file iconPDF (72 KB)  
    Freely Available from IEEE
  • 14/sup th/ IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2006

    Publication Year: 2005 , Page(s): nil12
    Save to Project icon | Request Permissions | PDF file iconPDF (93 KB)  
    Freely Available from IEEE
  • 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2006

    Publication Year: 2005 , Page(s): nil12
    Save to Project icon | Request Permissions | PDF file iconPDF (93 KB)  
    Freely Available from IEEE
  • Awards

    Publication Year: 2005 , Page(s): nil16
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • RTP Conference Achievement Awards

    Publication Year: 2005 , Page(s): nil13 - nil14
    Save to Project icon | Request Permissions | PDF file iconPDF (47 KB)  
    Freely Available from IEEE
  • Robert MacKnight [biography]

    Publication Year: 2005 , Page(s): nil15
    Save to Project icon | Request Permissions | PDF file iconPDF (390 KB)  
    Freely Available from IEEE
  • 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • Synthesis and control of ultra thin gate oxides for the 90 and 65 nm nodes

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2624 KB) |  | HTML iconHTML  

    Thin gate oxide processes for advanced semiconductor manufacturing present many challenges at both the 90 and 65 nm technology nodes. In most cases the films are oxynitride materials (SiOxNy) constructed in single wafer tools clustered on the same common platform. The combination of discrete process chambers and the atomic dimensions of the dielectric puts a premium on film characterization and process control. The electrical specifications are severe with common values of ±1 Å leading to nitrogen and oxygen dose requirements of better than ±5E14 at/cm2. In the recent past difficulties maintaining those specifications have repeatedly lead to tool down situations and limited run paths. In the aftermath of those events, the investigations which followed exposed weaknesses in both the metrology and the qualification strategies used to characterize those processes. In this paper, a number of examples will be presented which illustrate the sensitivity of the composite process to excursions in any of its component steps. The relative sensitivities of different in-line measurement techniques (optical, electrical, and chemical) will be reported and the data used to illustrate the clear advantages of in-line compositional analysis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS challenges of keeping up with Moore's Law

    Publication Year: 2005
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3435 KB) |  | HTML iconHTML  

    As the conventional scaling of CMOS technology is reaching its physical limitations, new materials and processes hold promise of giving CMOS a new lease on life. In order to turn an opportunity into a reality, the semiconductor industry is confronted with a daunting task of managing and co-integrating an unprecedented confluence of innovative approaches: high-k dielectric materials (HfO2, HfSiON) possibly to be formed by atomic layer deposition (ALD) are needed to curb gate leakage current and thus power consumption; metal gates (TiN, TaC, MoN) are requisite for optimization of threshold voltages for MOSFETs allowing low voltage operation; engineered substrates (sSOI, SiGeOI, GOI, dual substrate orientation) along with uni-axial and biaxial stressor techniques are required to keep the channel carrier mobility high to effect further performance gains; higher-mass dopant species (B10H14) are being synthesized to enable ultra-shallow junction; new dopant activation techniques (spike, pulsed laser anneals) and new contact metallization (NiSi) are pursued to induce high dopant activation and low contact resistance, respectively. The introduction of these innovative approaches is coming at a high price, though: the new materials pose new set of concurrent, multifarious challenges both for unit process development and for process integration. This paper reviews the technology opportunities and focuses on the trade-offs between performance benefits, scalability, complexity, co-integrability (including prominently spatial and temporal constraints on thermal processing), and impact on metrology, yield, and reliability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel fabrication process to realize ultra-thin (EOT = 0.7 nm) and ultra-low-leakage SiON gate dielectrics

    Publication Year: 2005
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2960 KB) |  | HTML iconHTML  

    The reaction mechanism of nitrogen atoms with Si was investigated based on first principles calculations and experimental results to realize ultra thin SiN-based SiON films with high insulation and good interfacial properties. Incorporation rate of nitrogen atoms into Si has a great influence on arranging 3-fold coordinated N atoms uniformly. By arranging 3-fold coordinated N atoms into the Si sub-surface layer uniformly, oxidation-resistant Si3N4 film can be formed and O atoms were successfully incorporated into the SiN/Si interface with minimum disruption of SiN structures. By using this novel process, a high-quality ultra-thin gate SiON film with an equivalent oxide thickness (EOT) of 0.7 nm and a leakage current (Jg) of 95 A/cm2, i.e., 1/10 or less than that of traditional SiON films was realized. Mobility is not reduced to less than 89% of an ideal SiO2 film View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis and Control of Ultra Thin Gate Oxides for the 90 and 65 NM Nodes

    Publication Year: 2005 , Page(s): 31 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2613 KB) |  | HTML iconHTML  

    Thin gate oxide processes for advanced semiconductor manufacturing present many challenges at both the 90 and 65 nm technology nodes. In most cases the films are oxynitride materials (SiOxNy ) constructed in single wafer tools clustered on the same common platform. The combination of discrete process chambers and the atomic dimensions of the dielectric puts a premium on film characterization and process control. The electrical specifications are severe with common values of plusmn1 Aring leading to nitrogen and oxygen dose requirements of better than plusmn5E14 at/cm2. In the recent past difficulties maintaining those specifications have repeatedly lead to tool down situations and limited run paths. In the aftermath of those events, the investigations which followed exposed weaknesses in both the metrology and the qualification strategies used to characterize those processes. In this paper, a number of examples will be presented which illustrate the sensitivity of the composite process to excursions in any of its component steps. The relative sensitivities of different in-line measurement techniques (optical, electrical, and chemical) will be reported and the data used to illustrate the clear advantages of in-line compositional analysis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Suppression of thermal interface degradation in high-k film/Si by helium

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4185 KB) |  | HTML iconHTML  

    Suppression of thermal interface degradation, especially silicidation, in high-k film (ZrO2, HfO2)/Si systems by a helium (He) process, which adds He gas during various annealing processes, was demonstrated. The high-k film/SiO2/Si thermal interface stability was investigated in terms of N2, and He gas annealing with controlled oxygen partial pressure (PO2) at 920degC. A comparison of N2 and He annealing with controlled PO2 revealed that the optimal PO2 ranges in He at which the thermal stability of a layered structure can be achieved are wider than that in N2. Moreover, regarding the poly-Si/SiO2/high-k film interface, it was found that He through process consisting of low-temperature SiH 4 flow diluted by He and high-pressure He post-annealing is the most effective means of suppressing silicidation, whereas a conventional N2 through process cannot. These results indicate that high-concentration He atoms are indispensable for the upper poly-Si/SiO2 interface. It is supposed that many He atoms physically obstruct SiO creation through the quenching of atomic vibration at the SiO2/Si interface, thus impeding the first step of the silicidation reaction View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Plasma doping and subsequent rapid thermal processing for ultra shallow junction formation

    Publication Year: 2005
    Cited by:  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1346 KB) |  | HTML iconHTML  

    Authors summarize and update the status of plasma doping (PD) using He plasma amorphous (PA) technology and spectroscopic ellipsometry (SE). Authors also recommend PD as the best alternative method for ultra shallow junction formation at the 45 nm technology node and beyond. The latest annealing methods of laser annealing (LA) and flash lamp annealing (FLA) were combined with PD. Conventional spike RTA was also used to achieve adequate junction depth with lower resistance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced thermal processing of semiconductor materials in the msec-range

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5721 KB) |  | HTML iconHTML  

    This paper reviews the advances that flash lamp annealing brings to the processing of the most frequently used semiconductor materials, namely silicon and silicon carbide, thus enabling the fabrication of novel microelectronic structures and materials. The paper describes how such developments can translate into important practical applications leading to a wide range of technological benefits. Opportunities in ultra-shallow junction formation, heteroepitaxial growth of thin films of cubic silicon carbide on silicon, and crystallization of amorphous silicon films, along with the technical reasons for using flash lamp annealing are discussed in the context of state-of-the-art materials processing View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced activation and stability of ultra-shallow junctions using flash-assisted RTP

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2643 KB) |  | HTML iconHTML  

    Advanced-logic device technology for the 65 nm node and beyond requires highly-activated, shallow, and abrupt dopant profiles (Int. Technol. Roadmap for Semicond., 2003). The combination of ion implantation and an advanced annealing technology is expected to provide solutions for these requirements. In contrast to spike annealing, a diffusion-less but highly activating, high-temperature, flash-assisted RTP annealing approach for the formation of ultra-shallow junctions will be demonstrated. The flash-assisted RTP technique is a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65 nm node and beyond (Gelpey, et al., 2002, McCoy, et al., 2004). The optimal process for high activation during flash-assisted RTP involves a temperature ramp-up to an intermediate temperature between 700degC and 900degC and, once the intermediate temperature is reached, a very short, intense flash on the front side of the wafer induces a temperature jump up to 1325degC with a peak width of approximately 1.6 ms in a 100 ppm oxygen in nitrogen gaseous ambient. In this paper, we will present some of our recent p+MOS and n+MOS results on the fabrication of ultra-shallow junctions using flash-assisted RTP in crystalline and pre-amorphized silicon. It will be shown that such junctions are suitable for future technology generations. The measured "mechanical/electrical" sheet resistance values of the junctions are compared to Hall measurements on the same samples to gain an insight into the reliability of the destructive four-point probe (4PP) method for such extremely shallow junctions. Deactivation studies will be presented to examine the stability of the process to the required subsequent thermal processes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005 , Page(s): 85
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2005 , Page(s): 85
    Save to Project icon | Request Permissions | PDF file iconPDF (30 KB)  
    Freely Available from IEEE
  • Ultra shallow junctions formed by sub-melt laser annealing

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1940 KB) |  | HTML iconHTML  

    Since the requirements for the S/D extensions for future devices become more and more severe with respect to activation and vertical abruptness, a huge effort has been done to develop ultra-fast annealing techniques such as laser annealing. Due to the fact that only the surface layers are heated, the Si wafer serves as a heat sink. Hence, extremely fast cooling rates can be obtained resulting in a high activation and limited diffusion of the dopants. We present a preliminary study on the activation of n- and p-type junction implants by sub-melt laser annealing. The influence of the pre-amorphization depth, the laser annealing temperature and other process parameters on the activation has been investigated. Sheet resistance and junction depth measurements reveal good activation with minimal diffusion View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.