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IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

Date 2-3 March 2006

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Displaying Results 1 - 25 of 94
  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Front Cover

    Publication Year: 2006, Page(s): c1
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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Title Page

    Publication Year: 2006, Page(s):i - iii
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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures

    Publication Year: 2006
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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Table of contents

    Publication Year: 2006, Page(s):v - xii
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  • Message from the General and Program Chairs

    Publication Year: 2006, Page(s): xiii
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  • Symposium committees

    Publication Year: 2006, Page(s): xiv
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  • Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems

    Publication Year: 2006, Page(s): 3
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  • Multiprocessor Systems-on-Chips

    Publication Year: 2006, Page(s): 4
    Cited by:  Papers (2)
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  • Floorplanning based on particle swarm optimization

    Publication Year: 2006
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB) | HTML iconHTML

    This paper presents a floorplanning method based on particle swarm optimization (PSO). We adopted the B*-tree floorplan structure to generate an initial stage with overlap free for placement and utilized PSO to find out the potential optimal placement solution. Unlike other related research, our method can avoid the solution from falling into the local minimal and has ability of more efficiency an... View full abstract»

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  • Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented channel matrix used in MIMO systems. The architecture concurrently addresses algorithm... View full abstract»

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  • Adaptive porting of analog IPs with reusable conservative properties

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (658 KB) | HTML iconHTML

    Analog layout automation is one of the most challenging subjects that has to cope with trade-offs among analog specific requirements such as noise, linearity, gain, supply-voltage, speed, power consumption, etc. This paper proposes a novel porting methodology that guides the reuse of analog IPs, followed by an automation system. The methodology introduces a concept of conservative properties that ... View full abstract»

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  • VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography

    Publication Year: 2006
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    With the advent of multi-million gate chips, field programmable gate arrays (FPGAs) have achieved high usability for design verification, exchange, test and even production. Adding to this is the possibility of reusing readily available licensed IP to shorten the design cycle. A major concern for IP owners is the possible over-deployment of the IP into more devices than originally licensed. In thi... View full abstract»

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  • Metal fix and power network repair for SOC

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (186 KB) | HTML iconHTML

    This paper shows the design flowchart to do metal fix in Chameleon CS2112. CS2112 is an integrated SOC system in one chip with a fabric circuit of 84 processors, 48 local memories, ARC processor, memory controller, PCI controller, DMA configuration subsystems and programmed I/Os. The first silicon failed due to the hold time problem at program I/Os and large IR drop at the center of the chip. The ... View full abstract»

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  • Multi-SP: a representation with united rectangles for analog placement and routing

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    In analog layout, the placement and routing are closely connected with each other in the optimization of the area, the parasitics, the mutability and so on. In this paper, we introduce a common data-structure to the placement and multilayer routing, where devices and wires are represented by united rectangles. It is called multi-layer sequence-pair (multi-SP). We also provide a bi-directional tran... View full abstract»

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  • Formulating the empirical strategies in module generation of analog MOS layout

    Publication Year: 2006
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    In module generation for analog cell layout, it is necessary to incorporate the designers' empirical techniques to achieve small area as well as high performance. This paper presents the formulation of two types of module generation problems, faithful to expert's empirical knowledge, to ease such incorporation. One is series module generation problem, where we introduce equivalent circuit modifica... View full abstract»

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  • An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessors

    Publication Year: 2006
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    The trends in advanced integrated circuit technologies require us to look for new ways to utilize large numbers of gates and reduce the effects of high interconnect delays. One promising research direction is chip multiprocessors that integrate multiple processors on the same die. Among the components of a chip multiprocessor, its memory subsystem is maybe the most critical one, since it shapes bo... View full abstract»

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  • High speed low swing dynamic circuits with multiple supply and threshold voltages

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full v... View full abstract»

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  • High performance service-time-stamp computation for WFQ IP packet scheduling

    Publication Year: 2006
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (269 KB) | HTML iconHTML

    In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network proce... View full abstract»

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  • Synthesis of pipelined SRSL circuits

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB) | HTML iconHTML

    In this paper, we propose a new design methodology for clockless circuits based on the present methodology of clocked circuits. This methodology takes advantage of the maturity of current CAD tools to synthesize new clockless pipelines without disrupting their design flow. Currently, there is no established design methodology to support the design and verification of clockless circuits. As a case ... View full abstract»

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  • An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standard

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (233 KB) | HTML iconHTML

    This paper proposes an adaptable receiver architecture for the WCDMA downlink UMTS standard. The architecture is aimed to support the receiver in such a way that it can self-adapt to different channel conditions. Architectural optimizations aiming to a more efficient implementation are presented and the advantages of the self-adaptable behavior of the receiver under a Rayleigh channel are shown View full abstract»

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  • Autonomous realization of Boeing/JPL sensor electronics based on reconfigurable system-on-chip technology

    Publication Year: 2006
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    This paper presents a reconfigurable architecture that is specifically tailored for the autonomous realization of the Boeing/JPL gyroscope and its interface circuitry. The overall architecture consists of a reconfigurable hardware substrate that suits the implementation of transposed form FIR filters and a custom non-stochastic search algorithm, which is in charge of autonomously providing the bes... View full abstract»

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  • Defect-aware design paradigm for reconfigurable architectures

    Publication Year: 2006
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to avoid defects. If nanotechnology based fabrications are applied, the yield may even go down to zero, as avoiding defects during fabrication will not be a feasible option. Hence, future architectures have to be defect-tolera... View full abstract»

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  • New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

    Publication Year: 2006
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (550 KB) | HTML iconHTML

    Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel archit... View full abstract»

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  • A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (626 KB) | HTML iconHTML

    Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to o... View full abstract»

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  • QUKU: a two-level reconfigurable architecture

    Publication Year: 2006
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (206 KB) | HTML iconHTML

    FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfiguration to adapt FPGA operation to changing application requirements has been hampered by slow reconfiguration times, and poor CAD tool support. In this paper, a new architecture, QUKU (pronounced cuckoo), is described wh... View full abstract»

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