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Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on

Date 2-3 March 2006

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Displaying Results 1 - 25 of 94
  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Front Cover

    Page(s): c1
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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Title Page

    Page(s): i - iii
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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures

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  • IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Table of contents

    Page(s): v - xii
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  • Message from the General and Program Chairs

    Page(s): xiii
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  • Symposium committees

    Page(s): xiv
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  • Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems

    Page(s): 3
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  • Multiprocessor Systems-on-Chips

    Page(s): 4
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  • Floorplanning based on particle swarm optimization

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB) |  | HTML iconHTML  

    This paper presents a floorplanning method based on particle swarm optimization (PSO). We adopted the B*-tree floorplan structure to generate an initial stage with overlap free for placement and utilized PSO to find out the potential optimal placement solution. Unlike other related research, our method can avoid the solution from falling into the local minimal and has ability of more efficiency and robustness for explored solution space. Experiments employing MCNC and GSRC benchmarks show that the performance of our method for placement by the ability of exploring better solutions. The proposed approach exhibited rapidly convergence and led to more optimal solutions than other related approach. View full abstract»

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  • Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system

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    Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented channel matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance. View full abstract»

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  • Adaptive porting of analog IPs with reusable conservative properties

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    Analog layout automation is one of the most challenging subjects that has to cope with trade-offs among analog specific requirements such as noise, linearity, gain, supply-voltage, speed, power consumption, etc. This paper proposes a novel porting methodology that guides the reuse of analog IPs, followed by an automation system. The methodology introduces a concept of conservative properties that are necessary and sufficient for the configuration of the high quality layout. The properties are extracted from schematics and the past layouts, and then are represented in terms of module configurations and topological constraints imposed on devices. In experiments, our porting system is applied to several industrial analog circuits. In the design of an A/D converter, we ported the layout on 0.20μm/3.3V technology to that on 0.18μm/1.8V technology. The result not only met the required performance, but also achieved the comparable quality with the manual layout. The design time was reduced drastically. View full abstract»

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  • VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography

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    With the advent of multi-million gate chips, field programmable gate arrays (FPGAs) have achieved high usability for design verification, exchange, test and even production. Adding to this is the possibility of reusing readily available licensed IP to shorten the design cycle. A major concern for IP owners is the possible over-deployment of the IP into more devices than originally licensed. In this paper, we propose a system based on both public-key and secret-key cryptography embedded in a secured design exchange protocol for protecting the rights of the IP owner. The system consists of hardware-supported design encryption and secured device authentication protocols. Design encryption based on secured device identification ensures that the IP can only be deployed into explicitly identified and agreed upon devices. The system uses a combination of secret and public-key cryptographic functions devised for an uncomplicated trustable design exchange scenario. The public-key functions use modular squaring (Rabin lock) on the FPGA chip instead of exponentiation to reduce the hardware complexity. View full abstract»

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  • Metal fix and power network repair for SOC

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    This paper shows the design flowchart to do metal fix in Chameleon CS2112. CS2112 is an integrated SOC system in one chip with a fabric circuit of 84 processors, 48 local memories, ARC processor, memory controller, PCI controller, DMA configuration subsystems and programmed I/Os. The first silicon failed due to the hold time problem at program I/Os and large IR drop at the center of the chip. The advantage of metal fixes will reduce the mask cost for bug fixing found in silicon. There are a couple of problems to be addressed in the post-silicon metal fixing. Make sure the simulation result in the old design to match the silicon measurement and the simulation setup provides the accuracy for metal fix to predict the performance in new silicon View full abstract»

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  • Multi-SP: a representation with united rectangles for analog placement and routing

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    In analog layout, the placement and routing are closely connected with each other in the optimization of the area, the parasitics, the mutability and so on. In this paper, we introduce a common data-structure to the placement and multilayer routing, where devices and wires are represented by united rectangles. It is called multi-layer sequence-pair (multi-SP). We also provide a bi-directional translation between a layout and a multi-SP under align-constraint. Since the multi-SP is geometry free, it enables us to manage diversified methodologies such as device sizing and technology migration. Also, it gives a way to take the parasitics between devices and wires of optimizing placement and routing simultaneously. We implemented a compaction tool based on multi-SP and showed its potential experimentally View full abstract»

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  • Formulating the empirical strategies in module generation of analog MOS layout

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    In module generation for analog cell layout, it is necessary to incorporate the designers' empirical techniques to achieve small area as well as high performance. This paper presents the formulation of two types of module generation problems, faithful to expert's empirical knowledge, to ease such incorporation. One is series module generation problem, where we introduce equivalent circuit modifications to maximize the diffusion merging and minimize the number of diffusion contacts. The other is the common-centroid module generation problem which is formulated as a mathematical optimization problem taking coincidence, symmetry, dispersion and compactness into consideration. A greedy algorithm is also presented to solve this problem View full abstract»

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  • An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessors

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    The trends in advanced integrated circuit technologies require us to look for new ways to utilize large numbers of gates and reduce the effects of high interconnect delays. One promising research direction is chip multiprocessors that integrate multiple processors on the same die. Among the components of a chip multiprocessor, its memory subsystem is maybe the most critical one, since it shapes both power and performance characteristics of the resulting design. Motivated by this observation, this paper addresses the problem of decomposing (partitioning) on-chip memory space across parallel processors and allocating data across memory components in an integrated manner. In the most general case, the resulting memory architecture is a hybrid one, where some memory components are accessed privately, whereas the others are shared by two or more processors. The proposed approach for achieving this has two complementary components: an optimizing compiler and an ILP (integer linear programming) solver. The role of the compiler in this approach is to analyze the application code and detect the interprocess or data sharing patterns, given the loop parallelization information. The job of the ILP solver, on the other hand, is to determine the sizes of the on-chip memory components, how these memory components are shared across multiple processors in the system, and what data each component holds. In other words, we address the problem of integrated memory space partitioning and data allocation for chip multiprocessors View full abstract»

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  • High speed low swing dynamic circuits with multiple supply and threshold voltages

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    A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to standard full-swing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption by up to 84.2% in the high fan-in domino gates. View full abstract»

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  • High performance service-time-stamp computation for WFQ IP packet scheduling

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    In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing platforms for line-rates beyond 200Gbps View full abstract»

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  • Synthesis of pipelined SRSL circuits

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    In this paper, we propose a new design methodology for clockless circuits based on the present methodology of clocked circuits. This methodology takes advantage of the maturity of current CAD tools to synthesize new clockless pipelines without disrupting their design flow. Currently, there is no established design methodology to support the design and verification of clockless circuits. As a case in study, the proposed design methodology targets the synthesis of new pipelines based on a recently introduced clockless design technique called self-resetting stage logic (SRSL). The synthesis of SRSL pipelines starts from a synthesized gate netlist to satisfy a specified data rate by minimizing overall pipeline area. Since this synthesis problem is formulated as a large integer programming problem, an efficient two-phase heuristic algorithm is proposed to solve this problem. Experimental results show that SRSL pipelines can reach throughputs in the GHz range and are highly suitable for coarse-grain datapaths View full abstract»

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  • An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standard

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    This paper proposes an adaptable receiver architecture for the WCDMA downlink UMTS standard. The architecture is aimed to support the receiver in such a way that it can self-adapt to different channel conditions. Architectural optimizations aiming to a more efficient implementation are presented and the advantages of the self-adaptable behavior of the receiver under a Rayleigh channel are shown View full abstract»

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  • Autonomous realization of Boeing/JPL sensor electronics based on reconfigurable system-on-chip technology

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    This paper presents a reconfigurable architecture that is specifically tailored for the autonomous realization of the Boeing/JPL gyroscope and its interface circuitry. The overall architecture consists of a reconfigurable hardware substrate that suits the implementation of transposed form FIR filters and a custom non-stochastic search algorithm, which is in charge of autonomously providing the best binary configuration on the adaptive hardware. Preliminary simulation results show that our architecture is able to cope with single hard errors that occur on the reconfigurable substrate, while power analysis demonstrates that the proposed methodology is capable of implementing filters that consume almost 4.5 times less power, compared with industrial application specific reconfigurable fabrics View full abstract»

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  • Defect-aware design paradigm for reconfigurable architectures

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    With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to avoid defects. If nanotechnology based fabrications are applied, the yield may even go down to zero, as avoiding defects during fabrication will not be a feasible option. Hence, future architectures have to be defect-tolerant. Most of the current defect-tolerance schemes introduce redundancy in architecture to combat defects. Alternatively we can introduce defect tolerance in the design-flow. In this paper we analyze the bottlenecks faced by current design-methodologies while addressing defect tolerance. We study the performance of present place and route tools on a defective fabric in terms of area and critical delay penalty, and explore routing aware placement in this context. We have proposed a new cost function, CA-RISA for improving the performance in a defect-aware environment View full abstract»

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  • New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

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    Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested on-demand and partial reconfiguration approaches for fine-grain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs View full abstract»

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  • A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm

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    Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology View full abstract»

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  • QUKU: a two-level reconfigurable architecture

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    FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfiguration to adapt FPGA operation to changing application requirements has been hampered by slow reconfiguration times, and poor CAD tool support. In this paper, a new architecture, QUKU (pronounced cuckoo), is described which uses a coarse-grained reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, while the high-speed CGRA reconfiguration is used within an application for operator re-use. An FIR filter kernel has been implemented on QUKU and is shown to have performance which bridges the gap between softcore CPUs and custom FPGA filter circuits View full abstract»

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