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Design Automation, 1994. 31st Conference on

Date 6-10 June 1994

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  • DAC '94 [Cover page]

    Publication Year: 1994, Page(s): c1
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  • DAC'94 Title Page

    Publication Year: 1994, Page(s): i
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  • DAC'94 Copyright Page

    Publication Year: 1994, Page(s): ii
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  • Executive Committee

    Publication Year: 1994, Page(s): iii
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  • General Chair's Message

    Publication Year: 1994, Page(s): iv
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  • Technical Program Committee

    Publication Year: 1994, Page(s):v - vi
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  • Awards pages

    Publication Year: 1994, Page(s):vii - ix
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  • Call for papers

    Publication Year: 1994, Page(s): x
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  • Reviewers

    Publication Year: 1994, Page(s):xi - xv
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  • 1994 Keynote Address

    Publication Year: 1994, Page(s):xvi - xvii
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (141 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Table of contents

    Publication Year: 1994, Page(s):xviii - xxviii
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  • Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems

    Publication Year: 1994, Page(s):1 - 4
    Cited by:  Papers (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (192 KB)

    Existing software scheduling techniques limit the functions that can be implemented in software to those with a restricted class of timing constraints, in particular those with a coarse-grained, uniform, periodic behavior. In practice, however, many systems change their I/O behavior in response to the inputs from the environment. This paper considers one such class of systems, called reactive real... View full abstract»

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  • Synthesis of Instruction Sets for Pipelined Microprocessors

    Publication Year: 1994, Page(s):5 - 11
    Cited by:  Papers (25)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (61 KB)

    We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitecture. In addition, the assembly code is generated to show how the application can be compiled with the synthesized instruction set. The design of instruction sets is formulated as a modified scheduling problem. A binary tupl... View full abstract»

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  • A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

    Publication Year: 1994, Page(s):12 - 17
    Cited by:  Papers (45)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (181 KB)

    We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N, where the variables correspond to state line probabilities. We show that the approximation method is within 3% of the exact Chapman-Kolmogorov method, but is orders of magnitude faster for large circuits. Previous... View full abstract»

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  • Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs

    Publication Year: 1994, Page(s):18 - 23
    Cited by:  Papers (47)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (240 KB)

    In this paper, we consider the problem of calculating the signal and transition probabilities of the internal nodes of the combinational logic part of a finite state machine (FSM). Given the state transition graph (STG) of the FSM, we first calculate the state probabilities by iteratively solving the Chapman-Kolmogorov equations. Using these probabilities, we then calculate the exact signal and tr... View full abstract»

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  • ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits

    Publication Year: 1994, Page(s):24 - 30
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (95 KB)

    We describe ASTRX/OBLX, a synthesis system that can size high-performance analog circuit topologies to meet usersupplied linear performance specifications without designer-supplied equations. We present synthesis results for a large suite of circuit benchmarks and show that, when compared to prior approaches, ASTRX/OBLX can synthesize high-performance circuits with up to 3 orders of magnitude less... View full abstract»

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  • Simultaneous Placement and Module Optimization of Analog IC's

    Publication Year: 1994, Page(s):31 - 35
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB)

    New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced on high-performance analog circuits by using simultaneous placement and module optimization. An algorithmic approach to module generation provides alternative sets of modules optimized with respect to area and performance but e... View full abstract»

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  • Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits

    Publication Year: 1994, Page(s):36 - 40
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (142 KB)

    A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems. View full abstract»

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  • Management Issues in EDA

    Publication Year: 1994, Page(s):41 - 47
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (119 KB)

    The Electronic Design Automation (EDA) industry has grown to around $2.5 billion in a span of about 10 years. The dynamics of this industry impacts firms involved in any form of electronic design. Effective management of the design automation function leads to significant competitive advantage. Yet, there has been very little published study in this area. This paper presents a unified framework wh... View full abstract»

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  • Panel: Executive Perspective and Vision of the Future of EDA

    Publication Year: 1994, Page(s): 48
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (8 KB)

    As design complexity continues to grow, engineering teams have become increasingly reliant on sophisticated electronic design automation (EDA) tools and technology. Unlike the past, much of this technology comes from commercial suppliers. Indeed, many electronics manufacturers are wholly dependent on commercial vendors. Are these suppliers vendors capable of keeping pace with the market's demands,... View full abstract»

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  • A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules

    Publication Year: 1994, Page(s):49 - 55
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (95 KB)

    Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially communicate in complex and intricate ways. When designing communicating asynchronous modules, several difficult problems arise. First, even if each individual module can be synthesized correctly, according to the environment... View full abstract»

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  • Basic Gate Implementation of Speed-Independendent Circuits

    Publication Year: 1994, Page(s):56 - 62
    Cited by:  Papers (47)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (136 KB)

    Existing methods for synthesis of speedindependent circuits under unbounded delay model have difficulties in combining the generality of formal approach with the practicality of the implementation architectures used at the logic level. This paper presents a characteristic property of the state graph specification, called Monotonous Cover requirement, implying its hazard-free implementation within ... View full abstract»

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  • A Modular Partitioning Approach for Asynchronous Circuit Synthesis

    Publication Year: 1994, Page(s):63 - 69
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an efficient modular partitioning approach for asynchronous circuit synthesis. This approach partitions a large circuit specification into smaller and manageable modules that drastically reduces the synthesis complexity. Experimental results with a large number of practical asyn... View full abstract»

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  • Performance Analysis Based on Timing Simulation

    Publication Year: 1994, Page(s):70 - 76
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    Determining the cycle time and a critical cycle is a fundamental problem in the analysis of concurrent systems. We solve this problemusing timing simulation of an underlying Signal Graph (an extension of Marked Graphs). For a Signal Graph with n vertices and m arcs our algorithm has the polynomial time complexity O(b/sup 2/m), where b is the number of vertices with initially marked in-arcs (typica... View full abstract»

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  • Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications

    Publication Year: 1994, Page(s):77 - 80
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (71 KB)

    The contribution of this paper is an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph,we efficiently derive a Boolean function whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This... View full abstract»

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