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Digest of Papers Microprocesses and Nanotechnology 2005

Date 25-28 Oct. 2005

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Displaying Results 1 - 25 of 155
  • [Cover]

    Publication Year: 2005, Page(s): C1
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  • [Title page]

    Publication Year: 2005, Page(s): i
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  • Copyright page

    Publication Year: 2005, Page(s): ii
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  • Preface

    Publication Year: 2005, Page(s): iii
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  • Conference committee

    Publication Year: 2005, Page(s):v - vi
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  • Award winners

    Publication Year: 2005, Page(s):vii - xi
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  • [Society related material]

    Publication Year: 2005, Page(s): xii
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  • Table of contents

    Publication Year: 2005, Page(s):xiii - xxiii
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  • Digest of papers [title page]

    Publication Year: 2005, Page(s): 1
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  • Panasonic's system LSI: towards the ubiquitous network society

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (95 KB)

    Summary form only given. Consumer is now biggest market for LSIs; also biggest electronics market. The convergence of many applications in the ubiquitous network society means that a single strong system level approach to design is essential for success. In SoCs' design, software is becoming the dominant engineering problem in terms of reliable implementation, with software engineering resources e... View full abstract»

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  • Advanced technology development at SEMATECH

    Publication Year: 2005, Page(s):4 - 5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    The development of advanced technology is significantly impacted by the cost and complexity of bringing it from research to manufacturing. SEMATECH, a global consortium of major semiconductor manufacturers, has evolved over the last two decades to address this and other challenges of the chip industry. In doing so, we have become deeply attuned to the necessity of honing our R&D activities in ways... View full abstract»

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  • Emerging alternative devices for CMOS and beyond

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (144 KB)

    According to the latest version of the ITRS roadmap, CMOS scaling is predicted to continue into 2020 with physical gate lengths down to 5 nm. Driving forces are increased performance with smaller devices, increased functionality for larger chips and decreased cost per function. However to reach the predicted targets, large R&D efforts are required since both physical and technological limitations ... View full abstract»

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  • EUV lithography development in the United States

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    The infrastructure required to support the first full-field extreme ultraviolet lithography (EUVL) exposure tools, is under active development at a number of U.S. universities, U.S. national laboratories, and at U.S. semiconductor consortia. These infrastructure development projects are targeting EUV-specific critical issues in the mask, mask handling, source, optics, and resist areas that must be... View full abstract»

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  • Hyper-NA imaging in ArF immersion lithography

    Publication Year: 2005, Page(s):10 - 11
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1344 KB) | HTML iconHTML

    ArF immersion lithography (Lin, 2004) has emerged as the primary solution for the manufacturing of semiconductor device for 65-nm half-pitch node and beyond. The immersion technique allows the design of projection optics with a numerical aperture that exceeds unity. Pure water is the preferred immersion fluid for the first generation of the immersion exposure tool. The water has good transmissivit... View full abstract»

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  • Characterization of 45 nm att-PSM lithography with a hyper-NA ArF tool

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    In the 45 nm half pitch node, a mask induced polarization effect is appeared. Also, this effect depends on optical diffraction orders. This is notable in an attenuated phase shift mask (att-PSM) rather than in a Cr binary mask (BIM). Diffraction efficiency is also different between dense patterns and larger pitch patterns. In lithography simulation, we have to use a rigorous method and to consider... View full abstract»

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  • Mask enhancer technology on ArF immersion tool for 45nm-node CMOS with 0.249μm2 SRAM contact layer fabrication

    Publication Year: 2005, Page(s):14 - 15
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (896 KB) | HTML iconHTML

    We achieve the contact layer printing of 0.249μm2 SRAM by using mask enhancer (ME) technology and 0.85NA ArF immersion tool. In conclusion, we strongly propose that ME is one of the most effective solutions to perform 45nm-node contact printing with sufficient lithographic performance for 45nm-node LSI manufacturing. View full abstract»

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  • Resist LER and LWR transfer during plasma etching processes for node 45 nm and beyond

    Publication Year: 2005, Page(s):16 - 17
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (824 KB) | HTML iconHTML

    As critical dimensions (CD) for semiconductor devices shrink to few tens of nanometers, the line edge roughness (LER) or line width roughness (LWR) becomes a critical issue because it can degrade resolution and linewidth accuracy (Yoshimura et al., 1993) and causes fluctuations of transistors performances (Croon et al., 2002). LER is currently calculated by performing "threshold" analysis. In this... View full abstract»

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  • Model-based OPC for resist reflow process

    Publication Year: 2005, Page(s):18 - 19
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (680 KB) | HTML iconHTML

    In this paper, model-based optical proximity correction (OPC) software for thermal reflow is introduced and verified for its accuracy in comparison with experiment results due to pitch sizes. For its purpose, the resist reflow process (RRP) is modeled, and the OPE effects after development and thermal reflow are described by using the top view images. The sensitivity of the optimized parameters fo... View full abstract»

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  • Newly developed RELACS process and materials for 65nm node device and beyond

    Publication Year: 2005, Page(s):20 - 21
    Cited by:  Papers (1)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1144 KB) | HTML iconHTML

    To meet market's demands for high performance devices, we have studied various resolution enhancement techniques (RET), such as off axis illumination, phase shift masks, optical proximity correction, resist thermal reflow, and chemical shrinkage process etc. RELACS (resolution enhancement lithography assisted by chemical shrink) is one of the most useful technology among chemical shrink processes.... View full abstract»

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  • Nanofabrication of inorganic structures utilizing biotechnology

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    Several research groups proposed the introduction of biomolecules into the semiconductor process (Yamashita, 2001; Hikono et al., 2003). We proposed the fabrication of key component of quantum electronic devices and named the process bio nano process (BNP). The first step is making inorganic or semiconductor nanoparticle (NP) or nanowire (NW) in the protein cavity by biomineralization. The second ... View full abstract»

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  • Highly ordered horizontally directional SWNTs grown by thermal CVD with a local electric field

    Publication Year: 2005, Page(s):24 - 25
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    Directional control of single-wall carbon nanotubes (SWNTs) is important for transistor application of SWNTs. It is reported that chemical vapor deposition (CVD) growth under a local electric field produces horizontally directed SWNTs (Zhang et al., 2001). The controllability of this process, however, is not yet well understood. In this report, we investigate how to improve the controllability in ... View full abstract»

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  • Nanocomposites of carbon nanotubes-gold nanoparticles for surface-enhanced Raman scattering

    Publication Year: 2005, Page(s):26 - 27
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    We describe the combination of carbon nanotubes (CNTs) and gold nanoparticle (GNPs) that can be used to investigate the enhancement ability of CNTs by using Raman spectroscopy. In this work, the CNTs were immersed in the GNPs solution and then annealing in the vacuum annealing furnace. The surface of CNTs provides free spaces for the adsorption of gold nanoparticles, so the nanocomposites of CNTs-... View full abstract»

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  • Position-controlled carbon nanotube growth on single iron nanoparticles prepared by electron beam-induced chemical vapor deposition

    Publication Year: 2005, Page(s):28 - 29
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (792 KB) | HTML iconHTML

    Position control during carbon nanotube (CNT) growth is critical for CNT device application. We have developed a technique for precisely positioning a single iron nanoparticle on a substrate using electron beam-induced chemical vapor deposition (EB-CVD) with ferrocene source gas. A single-walled carbon nanotube (SWNT) preferably grew on the iron nanoparticle. EB-CVD makes it possible to grow 3D na... View full abstract»

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  • Carbon nanotube composites for electrochemical sensing

    Publication Year: 2005, Page(s):30 - 31
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1216 KB) | HTML iconHTML

    This paper deals for the first time with outstanding properties of CNT incorporated into an epoxy polymer, forming an epoxy composite hybrid material as a new electrode with improved electrochemical sensing properties. This novel CNT-epoxy composite is simple, cheap and results in interesting electrode material. The preparation and characterization of this multifunctional material is discussed, an... View full abstract»

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  • Formation factors of watermark for immersion lithography

    Publication Year: 2005, Page(s):32 - 33
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (960 KB) | HTML iconHTML

    In the advanced lithography process, the immersion lithography technique has become important in order to achieve the high quality resist patterns less than 50nm. In this technique, some defects such as a watermark and a nanoscale bubble have been focused as the serious problems to be solved. In actual system of the immersion lithography, the micro droplets of the immersion liquid remains randomly... View full abstract»

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