By Topic

48th Midwest Symposium on Circuits and Systems, 2005.

7-10 Aug. 2005

Filter Results

Displaying Results 1 - 25 of 487
  • 48th MWSCAS - Welcome

    Publication Year: 2005, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (244 KB) | HTML iconHTML
    Freely Available from IEEE
  • 48th MWSCAS - Events

    Publication Year: 2005, Page(s):0_2 - 0_24
    Request permission for commercial reuse | PDF file iconPDF (883 KB)
    Freely Available from IEEE
  • 48th MWSCAS - Committees

    Publication Year: 2005, Page(s):0_25 - 1_7
    Request permission for commercial reuse | PDF file iconPDF (231 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2005, Page(s):1_9 - 1_56
    Request permission for commercial reuse | PDF file iconPDF (655 KB)
    Freely Available from IEEE
  • 2005 48th IEEE International Midwest Symposium on Circuits and Systems (IEEE Cat. No. 05CH37691)

    Publication Year: 2005
    Request permission for commercial reuse | PDF file iconPDF (224 KB)
    Freely Available from IEEE
  • Copyright

    Publication Year: 2005, Page(s): 1_79
    Request permission for commercial reuse | PDF file iconPDF (570 KB)
    Freely Available from IEEE
  • Robust op amp circuit realizations using tridiagonal state space forms

    Publication Year: 2005, Page(s):1 - 4 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    The standard controllable and observable canonical realizations have A-matrices whose eigenvalue locations are highly sensitive to small perturbations to the nonzero entries of the A-matrix that correspond to the coefficients of the characteristic polynomial. On the other hand, the eigenvalue locations of tri-diagonal A-matrices are relatively insensitive to similar perturbations. Given a SISO tra... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An operational transconductance amplifier in 0.18/spl mu/m SOI

    Publication Year: 2005, Page(s):5 - 8 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (615 KB) | HTML iconHTML

    An operational transconductance amplifier (OTA) using three cascaded comparator stages is presented in 180nm fully depleted silicon on insulator (FDSOI) technology processed at MIT Lincoln Laboratory. Each comparator stage used 14 transistors with close to minimum aspect ratios. The OTA is self-biasing without the need for external bias circuitry, and provides a rail to rail input common mode rang... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Three transistor exponential transconductor

    Publication Year: 2005, Page(s):9 - 12 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (837 KB) | HTML iconHTML

    This work presents a novel exponential transconductor which is formed with only three NMOS transistors working in weak inversion. The circuit is biased with a single current source favoring the design of low voltage circuits and it can have a bias voltage from 1.2V and lower. An important circuit characteristic resides on his high performance output range feature, which is maintained up to 10muA t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An information theoretic approach to optimal amplifier operation

    Publication Year: 2005, Page(s):13 - 16 Vol. 1
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB) | HTML iconHTML

    Amplifier performance can be severely degraded by the presence of intrinsic physical noise sources. We analyze the information transfer rates for simple and wide-range operational transconductance amplifiers (OTAs) using the principles of information theory. Frequency transfer characteristics and input-referred noise of both simple and wide-range OTAs are modeled using process dependent noise para... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Current mode sense amplifier

    Publication Year: 2005, Page(s):17 - 20 Vol. 1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB) | HTML iconHTML

    In modern SRAMs, sense amplifiers are used to amplify the bit line swing in order to decrease access time. This paper seeks to present some new designs to improve the input and output impedance of the current mode sense amplifier. Two distinct groups of architectures are evaluated, and simulations were conducted for each group. Their performances are evaluated and compared View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wide gm adjustment range highly linear OTA with programmable mirrors operating in triode mode

    Publication Year: 2005, Page(s):21 - 23 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB) | HTML iconHTML

    A new very compact and highly linear CMOS OTA, with very wide gain tuning range, is presented. It uses a fixed gain linear V-I converter input stage and electronically programmable current mirrors working in triode which are very compact and continuously adjustable. Programmability is achieved by tuning VDS of the mirroring transistors. The OTA input range and bandwidth is approximately independen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A frequency-domain approach to polynomial function based interpolation

    Publication Year: 2005, Page(s):24 - 27 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB) | HTML iconHTML

    We present a kernel with block structure realized in the Farrow structure form. The design problem of kernel for sampling rate converter using the block structures becomes a nonlinear problem, because the product of the coefficient of the polynomial which constructs each block and the coefficient which determines the ratio of each block need. In this paper, hence, we propose the method for solving... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of symmetrical components in time-domain

    Publication Year: 2005, Page(s):28 - 31 Vol. 1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB) | HTML iconHTML

    This paper presents a novel system for estimating the symmetrical components of a three-phase set of signals in the time-domain. Symmetrical components are significant in the area of power systems and they are used for analysis, design, control and compensation purposes. Viewed in the context of signal processing, the symmetrical components are all located at a single frequency in the frequency sp... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A method for analysis of harmonics and inter-harmonics

    Publication Year: 2005, Page(s):32 - 35 Vol. 1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB) | HTML iconHTML

    A method for analysis of signals containing harmonics and inter-harmonics is presented and discussed. This method is primarily developed for analysis of power system signals which contain harmonic and inter-harmonic components. However, usefulness of the proposed technique goes beyond the area of power systems and it can be employed for other applications which require accurate and adaptive extrac... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The performance of the fixed-point least mean kurtosis and noisy inputs

    Publication Year: 2005, Page(s):36 - 38 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Since the optimal solution of the least mean kurtosis (LMK) is selected to minimize the negative of the kurtosis of the error signal, the noise that has symmetrical probability density function (PDF) does not affect the optimal solution. The LMK algorithm has been studied and proved to outperform the widely used LMS algorithm. Extending the previously proposed analyzing method to predict the perfo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Blind separation of mixed kurtosis signals using local exponential nonlinearities

    Publication Year: 2005, Page(s):39 - 42 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    In this paper we propose exponential type nonlinearities in order to blindly separate instantaneous mixtures of signals with symmetric probability distributions. These nonlinear functions are applied only in a certain range around zero in order to ensure the stability of the separating algorithm. The proposed truncated nonlinearities neutralize the effect of outliers while the higher order terms i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel inequality property of the second-order modes of linear continuous-time state-space systems

    Publication Year: 2005, Page(s):43 - 46 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (229 KB) | HTML iconHTML

    This paper reveals a novel inequality property of the second-order modes of linear continuous-time state-space systems. It is shown that, in the family of state-space systems having identical denominator polynomials and magnitude responses, the minimum phase system has the smallest second-order modes while the maximum phase system has the largest second-order modes. It is also shown that the secon... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction

    Publication Year: 2005, Page(s):47 - 50 Vol. 1
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB) | HTML iconHTML

    In this paper, we designed a four-parallel intra prediction architecture applied with four optimization schemes. Category-level interleaved scheme (CLIS) eliminates the bubble cycles of 14MB reconstruction. Mode-level scheduling (MLS) and early data preparation scheme (EDPS) rearrange the processing sequence of intra modes. The hardware resource of earlier low-complexity modes is used to deal with... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power ALU cluster design for media streaming architecture

    Publication Year: 2005, Page(s):51 - 54 Vol. 1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB) | HTML iconHTML

    This paper presented a low power ALU cluster design for media streaming processor, which combines the low-power circuitry design methodology and media streaming architecture. The experimental result shows the power and energy consumption of selected benchmark for multi-media and base-band communication systems can be reduced for 62% and 33% as well. In the mean time, both power dissipation and ene... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table

    Publication Year: 2005, Page(s):55 - 58 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (250 KB) | HTML iconHTML

    This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ePAPP: a gigabit embedded protocol analyzer pre-processor

    Publication Year: 2005, Page(s):59 - 62 Vol. 1
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (274 KB) | HTML iconHTML

    Network has been growing rapidly in both transmission bandwidth and transmission speed. This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network packets. It replaces the software protocol analysis program running on processors, with a significan... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a single chip block coder for the EBCOT engine in JPEG2000

    Publication Year: 2005, Page(s):63 - 66 Vol. 1
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    The main challenge in the VLSI design of an efficient JPEG2000 hardware is the block coder (BC) engine for the embedded block coding with optimised truncation (EBCOT). In this paper, we present the VLSI design of a BC system that can process 21 mega pixels per second. For the bit plane coder (BPC), we employ a concurrent symbol processing (CSP) algorithm to process of all 4 sample locations within... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesizing hashing circuits

    Publication Year: 2005, Page(s):67 - 70 Vol. 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    An approach for hardware synthesis of hashing transformations is presented, where the prescribed features that define a secure transformation are enforced by the design rules. This approach is fundamentally different from that adopted in implementations like SHA-1 or MD5, which are based on first devising an algorithm, and then analyzing it, with possible further modifications until arriving at a ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floating-gates transistors for precision analog circuit design: an overview

    Publication Year: 2005, Page(s):71 - 74 Vol. 1
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (303 KB) | HTML iconHTML

    This paper presents an overview of floating-gate transistors with an emphasis on using them as programmable elements to correct mismatch inherent in analog circuit design. The design methodology is such that floating-gate MOSFETs play the role of programmable elements while forming an inherent part of the circuitry of interest, as well. Such an approach results in a compact architecture with minim... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.