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2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)

28-30 Sept. 2005

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  • 2005 International Conference on Reconfigurable Computing and FPGAs ReConFig 2005

    Publication Year: 2005, Page(s): c1
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  • 2005 International Conference on Reconfigurable Computing and FPGAs - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 2005 International Conference on Reconfigurable Computing and FPGAs - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 2005 International Conference on Reconfigurable Computing and FPGAs - Table of contents

    Publication Year: 2005, Page(s):v - vii
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  • Preface

    Publication Year: 2005, Page(s): viii
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  • Organizing Committee

    Publication Year: 2005, Page(s): ix
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  • Program Committee

    Publication Year: 2005, Page(s): x
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  • Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling

    Publication Year: 2005, Page(s):8 pp. - 1
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1181 KB) | HTML iconHTML

    One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one... View full abstract»

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  • An image comparison circuit design

    Publication Year: 2005, Page(s):8 pp. - 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB) | HTML iconHTML

    Solder paste deposit on printed circuit boards is a critical stage. It is known that about 60% of defects in function, in this type of boards, are due to poor solder paste printing. These defects can be avoided by means of optical inspection of this printing. However, such an inspection is a tedious and intensive labor for human inspectors. In this work we propose to implement an image comparison ... View full abstract»

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  • FPGA-based customizable systolic architecture for image processing applications

    Publication Year: 2005, Page(s):8 pp. - 3
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (898 KB) | HTML iconHTML

    The present work focuses on the development of a reconfigurable systolic-based architecture for low-level image processing. The architecture is customizable providing the possibility to perform window operations for masks of 3 times3, 5 times5 and 7 times7 coefficients. A 2D systolic array of processing elements have been implemented, based on parallel modules with internal pipeline operation wher... View full abstract»

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  • An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method

    Publication Year: 2005
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    In this paper, an FPGA arithmetic logic unit architecture for computing elliptic curve scalar multiplication over the binary extension field GF(2163) is presented. The proposed architecture implements a parallel version of the half-and-add method using the mixed-coordinate representation for point addition, point doubling and point halving primitives. This way, our design can perform el... View full abstract»

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  • Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform

    Publication Year: 2005, Page(s):5 pp. - 5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    Discrete wavelet transform is a powerful mathematical tool used for signal and image compression, nonlinear filtering or noise reduction, signal and biomedical image processing and all kind of applications that implies a time-located variation on signals. The development of a hardware signal processing unit for the discrete wavelet transform for computing one-dimensional variable-length input data... View full abstract»

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  • A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays

    Publication Year: 2005
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    General purpose processors (GPPs) and ASICs have traditionally been the common means for building and implementing artificial neural networks (ANNs). However such computing paradigms suffer from the constant need of establishing a trade-off between flexibility and performance. Due to the technological advance in the development of programmable logic devices, field programmable gate arrays (FPGAs) ... View full abstract»

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  • Rapid prototyping of a self-timed ALU with FPGAs

    Publication Year: 2005
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    This article presents the design and implementation of a self-timed arithmetic logic unit (ALU) that has been developed as part of an asynchronous microprocessor. This displays an inherent operational characteristic of low consumption, owing to the synchronization signals that stop when the execution of an operation finishes (stoppable clock); that is to say, the dynamic consumption is zero, while... View full abstract»

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  • FPGA implementation of a synchronous and self-timed neuroprocessor

    Publication Year: 2005
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    This article presents the implementation of a neuroprocessor based on a self-organizing map (SOM) architecture. The processor presents a hybrid structure both synchronous and self-timed. Where the neuronal network blocks (SOM) are synchronized with a protocol of 4 phases, for the control of data flow. The neuroprocessor was designed for the analysis and classification of tension deformation patter... View full abstract»

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  • On the design of two-level reconfigurable architectures

    Publication Year: 2005, Page(s):8 pp. - 9
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (234 KB) | HTML iconHTML

    In this paper we study a fundamental design problem for 2-level reconfigurable architectures (which are a special case of hyperreconfigurable architectures). On the lower reconfiguration level such architectures perform ordinary dynamic reconfiguration operations. On the upper level they can dynamically change the reconfiguration capabilities of the reconfigurable resources that are available for ... View full abstract»

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  • A secure self-reconfiguring architecture based on open-source hardware

    Publication Year: 2005, Page(s):7 pp. - 10
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB) | HTML iconHTML

    With the new and powerful field programmable gate array (FPGA) families, new possibilities have been opened. One of these features is the possibility of reconfiguring a section of the FPGA while the rest is working. Moreover, this fixed part could be responsible for reprogramming the reconfigurable part, either because a change in functionality is required or because a new version of the hardware ... View full abstract»

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  • Platform for intrinsic evolution of analogue neural networks

    Publication Year: 2005, Page(s):8 pp. - 11
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (179 KB) | HTML iconHTML

    The goals of this research are to examine the possibility of intrinsically evolving analogue neural networks on a field programmable analogue array (FPAA). This paper discusses initial progress in this area by detailing the hardware implementation of three reconfigurable neuron models on an FPAA. Also discussed are possible techniques to allow dynamic reconfiguration of network connectivity and th... View full abstract»

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  • High quality uniform random number generation for massively parallel simulations in FPGA

    Publication Year: 2005, Page(s):8 pp. - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB) | HTML iconHTML

    This paper details the design and implementation of three uniform random number generators for use in massively parallel simulations in FPGAs. The three different generators are tailored to make use of three different types of hardware resource: logic, RAM, and DSP blocks. This allows the random number generator to be fitted into resources left-over after the main application has been written. The... View full abstract»

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  • VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks

    Publication Year: 2005, Page(s):8 pp. - 13
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    The inherent parallelism of artificial neural networks (ANNs) introduces several difficulties for its software implementation because of the sequential nature of von Neumann architectures. In contrast, hardware implementations offer the possibility to explore the massive parallelism implicit in this model. Also, due to the dynamic nature of ANN's synapses, a flexible hardware platform is required ... View full abstract»

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  • Quartz: a framework for correct and efficient reconfigurable design

    Publication Year: 2005, Page(s):8 pp. - 14
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (150 KB) | HTML iconHTML

    We present Quartz, the first language supporting advanced features such as polymorphism, overloading, formal reasoning and generic VHDL library compilation, for correct and efficient reconfigurable design. Quartz is designed to support formal reasoning for design verification and generic optimisation strategies can be captured as algebraic transformations; the correctness of such transformations h... View full abstract»

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  • Design space exploration of coarse-grain reconfigurable DSPs

    Publication Year: 2005, Page(s):8 pp. - 15
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    This work introduces a new digital signal processor (DSP) architecture concept, which provides increased instruction-level parallelism (ILP), flexibility and scalability compared to state-of-the-art DSPs. The concept can be characterized by an enhanced RISC microprocessor with a tightly coupled reconfigurable ALU array, a vector load/store unit and a control flow manipulation unit. These units imp... View full abstract»

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  • Optimizing register binding in FPGAs using simulated annealing

    Publication Year: 2005, Page(s):8 pp. - 16
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    When variables are assigned to registers or memories in FPGAs, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional units are writing to the same storage unit. Since in FPGAs the area covered by multiplexers is significantly large compared with the area of the overall design, reducing the area of the m... View full abstract»

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  • An FPGA-based parallel sorting architecture for the Burrows Wheeler transform

    Publication Year: 2005
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    Burrows-Wheeler transform (BWT) has received special attention due to its effectiveness in lossless data compression algorithms. However, implementations of BWT-based algorithms have been limited due to the complexity of the suffix sorting process applied to the input string. Proposed solutions involve data structures combined with hardware architectures aimed at reducing computational complexity.... View full abstract»

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  • Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices

    Publication Year: 2005, Page(s):6 pp. - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    Success has been demonstrated previously in the use of genetic algorithms (GAs) for autonomous fault-handling in field programmable gate array (FPGA) devices, yet the completeness of a given repair can be improved. This research explores extensions to voting systems to work in parallel with imperfect GA solutions for local permanent damage faults in the FPGA fabric. The benefits are evaluated by c... View full abstract»

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