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Microelectronics, 2005. ICM 2005. The 17th International Conference on

Date 13-15 Dec. 2005

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  • [Cover]

    Page(s): C1
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  • Proceedings. The 17th ICM 2005. 2005 International Conference on Microelectronics (IEEE Cat. No.05EX1112C)

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  • Copyright page

    Page(s): iv
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  • Table of contents

    Page(s): v - x
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  • Other messages

    Page(s): xi
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  • Conference committee

    Page(s): xii
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  • Conference committee

    Page(s): xiii
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  • [Breaker page]

    Page(s): xv
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  • Fiber-Optic Sensing Systems: Fiber-Bragg Grating Sensor and Swept Laser Interrogation Platform

    Page(s): xvi - xvii
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    • Introduction to Fiber-Optic Sensing • Focus on Fiber Bragg Grating Sensors • Sensor Interrogation Systems • Applications and Field Studies This presentation will focus on key technology components in a Fiber Bragg Grating (FBG) sensing system, including sensor design and construction, interrogation techniques, system integration, and data processing. Fiber Bragg Grating (FBG) sensing systems have emerged to be a practical technology for strain sensing, and are now deployed in a wide variety of applications including health monitoring of civil structures (highways, bridges, buildings, and dams), long-term fatigue assessment in ship hulls, and oil well pressure/temperature monitoring. Moreover, myriad potential applications are under active development, such as smart structures for aerospace vehicles, remote monitoring applications in nuclear plants, power cables, pipelines, and tow-arrays, as well as bio-medical and chemical sensing for trace pollutants, toxic gases, and in vivo temperature profiling in human bodies. FBG sensors are superior in their signal processing simplicity as the information is directly obtained by detecting Bragg wavelength shifts induced by the measurands. The FBG wavelength shift is directly proportional to the induced strain, temperature variation, or refractive index profile. For mechanical sensing, strain and temperature are the typical direct measurands. For sensing electromagnetic fields or bio-chemical agents, the FBGs would be integrated with appropriate materials to tranfer sensing parameters to temperature, strain, or refractive index changes. View full abstract»

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  • 3D TCAD Simulation of nanoscale Multi-Gate FETs (MuGFETs)

    Page(s): xviii
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    Aggressive scaling of bulk MOS device dimensions has been the major contributor driving improvements in integrated circuit performance. Due to limitations on gate oxide thickness, and source/drain junction depth, further scaling of MOSFET devices in the sub-50 nm process generation will be difficult, if not impossible. New device architecture and new material combinations are therefore needed to overcome technological challenges. Despite the added process complexity, double (FinFET) or triple (Tri-Gate) gate Multi-Gate FET (MuGFET) devices are emerging as strong candidates for low power or high performance applications in the future. This work report on the theoretical design evaluation of MuGFETs using commercial three-dimensional (3D) TCAD simulation tool. Because of three dimensional geometry of MuGFETs and complex channel profiles required to adjust the threshold voltage beyond 50 nm gate length, conventional 1D or 2D TCAD (process and device simulation) simulations are not directly applicable and hence not suited well from the point of view of accuracy and predictability. All critical process steps (i.e., channel implant, gate oxide growth, extension implant, halo implant, spacer formation and source-drain implant) for tri-gate MuGFETs on standard SOI have been included in the process simulation. The total number of mesh points for the half-device was approximately 180,000, while the processing time was 10-12 hours. Device simulations have been performed using drift diffusion model taking into account quantum confinement effects, bandgap narrowing effects, low field (doping and temperature dependence) and high field mobility models including surface scattering model of Lombardi. View full abstract»

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  • The Quest for Reliable Nano Computations

    Page(s): xix
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    In this presentation, we explore the feasibility of designing reliable nano-architectures using practical (i.e. very small = "less than 10") redundancy factors. To this end, we begin with a thorough review of redundant design strategies for fault-tolerant nano-architectures. We then adapt three redundant design strategies -- modular redundancy, von Neumann multiplexing, and reconfigurability -- to majority-gate circuits, and analytically evaluate these designs' reliabilities for very small redundancy factors (including fractional factors), using arguments as needed. This analysis motivates several extensions that allow optimization of reliability for very small redundancy factors, and highlights the benefit of using majority-gates in nano-scale design, paving the way for practical fault-tolerant architectures. Besides reliability, we simultaneously address low-power designing, and show that high-performance circuits can be operated reliably at ultra low switching energies. View full abstract»

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  • Monolithic Microwave Integrated Circuit

    Page(s): xx
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    Monolithic microwave integrated circuits (MMIC) are now part of most modern radars, communication systems and hand held devices, and current trends show that this technology will continue to play an important role in radar and communication systems in the foreseeable future. In monolithic microwave integrated circuits, microwave circuit design techniques are used to realize amplifiers, oscillators, mixers, or functional blocks, with the help of active devices, distributed transmission lines and or lumped elements. These circuits may be based on GaAs, silicon or SiGe technology, each having its own advantages and limitations. This talk will provide an introduction to the devices, circuits, and processes that go into the design and fabrication of these integrated circuits. View full abstract»

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  • Reconfigurable SOC Platforms

    Page(s): xxi
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    Reconfigurable VLSI platforms in the form of Field Programmable Gate Arrays have given a fresh impetus to the system-on-chip paradigm. New and exciting directions in VLSI design in the form of Hardware/Software co-design, on-the-fly configurable CPU cores and scalable architectures for complex multimedia applications have all started to appear. This talk will provide an overview of the recent advances in the design of SOC with particular reference to `design-for-reconfiguration' concept. Much like design-for-test, the design space for VLSI now includes considerations for future modifications, power reduction and amalgamation of software in different tools and design-flow. Some design techniques for complex SOC platforms will be discussed along with methods for mixed-signal design and implementation. View full abstract»

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  • [Breaker page]

    Page(s): 1
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  • An Elaborate Design and Optimization of Low Order Bandpass Sigma-Delta Modulator

    Page(s): 2 - 5
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    This paper presents an elaborate plan and optimization method for designing and implementing low-order band pass digital sigma-delta modulator with high order output dynamic range (DR). The noise suppression in the pass band region of the modulator and high order output DR would be achieved by designing and optimizing the Noise Transfer Function (NTF) based on over sampling ratio (OSR) and desired modulator operational frequency and designing the Signal Transfer Function (STF) by the mean which the optimum gain in desired frequency would be acquired. Designed and optimized modulator has been implemented completely on digital circuits and it would be shown that the first order designed modulator has the output dynamic range of 90dB which corresponds to 15 bits data conversion. Results from various simulations illustrate both the stability and high performance of the design and flexibility of the overall structure. View full abstract»

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  • A CMOS Fully Differential Σ - Δ A Frequency Synthesizer for 2-Mb/s GMSK Modulation

    Page(s): 6 - 9
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    A CMOS fully-differential 2.4-GHz Σ-Δ frequency synthesizer for Gaussian Minimum Shift Keying (GMSK) modulation is presented in this paper. The pre-compensation fractional-N PLL is adopted in the modulator. The designed circuits are simulated in a 0.18μm 1P6M CMOS process. The power consumption of the PLL is about 11-mW and the data rate of the modulator can get to 2-Mbits/s. View full abstract»

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  • A CMOS Voltage Reference Based on Threshold Voltage for Ultra Low-Voltage and Ultra Low-Power

    Page(s): 10 - 12
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    This work describes a CMOS voltage reference using only resistors and transistors working in weak inversion, without any bipolar transistors. The circuit operation is similar to bandgap references, but the voltage reference is given by the threshold voltage of an nMOS transistor. The circuit was implemented in a standard 0.35μm TSMC CMOS process. The circuit generates a reference of 514mV for a power supply of just 900mV and presents a 20 ppm/°C variation for the range of 0°C a 100°C. View full abstract»

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  • An Efficient Forward Biasing Body Bias Generator for Clock Delayed Domino Logic

    Page(s): 13 - 18
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    A technique for improving domino logic is to use a variable threshold voltage keeper (VTVK), so that the keeper size may be increased to improve the noise-immunity without significantly increasing the power and the delay. In this work, a novel body bias generator with forward biasing capability is proposed for the VTVK scheme. Forward biasing the keeper source-body junction allows its threshold voltage to be lowered more than the zero-bias case. The advantages of this work over previous ones are single supply operation, and lower power delay product. The simulation results for a 0.18 μm CMOS technology show an improvement between 20% and 50% in power delay product at 10°C and 80°C respectively, over its previous counterpart. View full abstract»

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  • Guide line for standard CMOS traveling wave amplifier design

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    Design of traveling wave amplifier (TWA) in 0.13μm standard CMOS technology is presented. Modelling of 80 Ω coplanar wave guide used to synthesize inductors TWA's lines is presented. Asymmetric cascode, CPW and losses compensation technique allow to maximize the TWA amplifier bandwidth. Simulations with design kit and developed models for CPW show a 52 GHz bandwidth with a maximum power gain of 10 dB for a 84 mW power consumption. Size of the layouted chip is 2.6 × 0.6mm2. View full abstract»

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  • Design of Low-Voltage MOSFET-Only Switched-Capacitor Filters

    Page(s): 24 - 29
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    A 1.8-V switched-capacitor (SC) and a 1-V switched-opamp (SO) filter in standard digital CMOS technology is presented. The filters use substrate-biased MOSFETs in depletion region as capacitors linearized by parallel compensation technique. The simulation results confirm the capability of compensated depletion-mode MOS capacitors to fulfill analog circuit requirements at low supply voltages. A novel SO biquadratic structure is also presented to realize high-Q filter specifications. At a 1.8-V supply, the SC filter achieves - 40 dB THD, and at a 1-V the SO filter has -46.3 dB THD in 0.18-μm CMOS process. View full abstract»

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  • High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS

    Page(s): 30 - 35
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    In this work, a high-speed full swing driver for large capacitive-loads for low-voltage CMOS applications is presented. The driver which has multi-path for driving the load has a low gate leakage. It works similar to a standard CMOS gate and can be implemented in any CMOS fabrication technology. The circuit does not use extra bootstrap capacitors, has a small effective input capacitance, and can operate in a wide range of supply voltages. Analytical expressions for the sizing of the transistors which should be determined for any load capacitance are also presented. The driver is compared to the previously proposed circuits in a 65 nm CMOS technology using HSPICE simulations. The results show that the circuit operates 20% faster than the previous drivers and its gate leakage is about half of the gate leakage of bootstrap drivers. View full abstract»

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  • Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture

    Page(s): 36 - 39
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    A low-power, high speed direct digital frequency synthesizer (DDFS) is presented. Some approximations are used to avoid using a large ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the compressed ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a DDFS has been implemented using Taylor's series. The spurious-free dynamic range is about 40 decibels at low synthesized frequencies. View full abstract»

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  • Design of a two stage Low Noise Amplifier at Ku Band

    Page(s): 40 - 45
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    Designing a Low Noise amplifier (LNA) at Ku band requires a lot of concerns to be taken care of. Circuits at this high frequency deviate from their normal behavior and are not very easy to implement. We have designed and implemented a LNA at 16 GHz and different issues regarding simulations and implementation have been discussed. The design specifications for this amplifier were not very demanding (compared to industry) due to the nature of it being a first time design. However, most of the specifications were met. We have discussed the design at 16 GHz with noise figure < 2.0 dB and a gain of 20dB. The built amplifier performed extremely well on the tests of gain, return loss, and noise figure. There was no oscillation present at the time of final testing which satisfies one requirement of amplifier design. The measured results show noise figure of 1.9 dB and gain of 20.57 dB which are according to our design requirements. View full abstract»

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  • Impact of high DC bias on RF LDMOS reliability for radar application

    Page(s): 46 - 49
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    The reliability of power RF LDMOS submitted to RF and DC accelerated tests under high temperature has been investigated by DC and dynamic electrical characterization. After DC and RF ageing, some electrical parameters changed, with a significant drift of the feedback capacitance (CRS). In order to explain qualitatively electrical parameter shifts, a 2D RF LDMOS structure was implemented and simulated with ATLAS-SILVACO. Simulation results tend to show that, for a given bias conditions, all conditions are set for hot carrier degradation. View full abstract»

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  • A low power, high SFDR, ROM-less direct digital frequency synthesizer

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    This paper describes the design of a ROM-less direct digital frequency synthesizer. The spurious free dynamic range (SFDR) of the proposed DDFS system is -91.51dBc. A DDFS IC has been designed in HP 0.5μm standard N-Well CMOS process technology, and that's layout has 2.489mm2 area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz. View full abstract»

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