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Design Automation, 1989. 26th Conference on

Date 25-29 June 1989

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  • DAC '89 [Cover page]

    Publication Year: 1989, Page(s): c1
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  • DAC'89 Title Page

    Publication Year: 1989, Page(s): i
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  • DAC'89 Copyright Page

    Publication Year: 1989, Page(s): ii
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  • Executive Committee

    Publication Year: 1989, Page(s): iii
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  • General Chair's Message

    Publication Year: 1989, Page(s): iv
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  • 1989 Program Committee

    Publication Year: 1989, Page(s): v
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  • Awards pages

    Publication Year: 1989, Page(s):vi - vii
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  • Call for papers

    Publication Year: 1989, Page(s): viii
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  • Advance Registration Form - 27th Design Automation Conference

    Publication Year: 1989, Page(s): ix
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  • Reviewers

    Publication Year: 1989, Page(s):x - xii
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  • Table of contents

    Publication Year: 1989, Page(s):xiii - xxiii
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  • The Last Decade of Design Automation. And the next.

    Publication Year: 1989, Page(s):xxv - xxvi
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  • Scheduling and Binding Algorithms for High-Level Synthesis

    Publication Year: 1989, Page(s):1 - 6
    Cited by:  Papers (63)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques by making use of a global priority function. A new design-space exploration technique, which combines this algorithm with an existing one based on time constraints, is also presented. A second algorithm is used for registe... View full abstract»

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  • A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs

    Publication Year: 1989, Page(s):7 - 12
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1121 KB)

    The paper describes a new algorithm for the scheduling and resource allocation problem in high-level synthesis. The algorithm can not only efficiently treat flattened signal flow graphs, but also handles graphs with embedded control constructs such as conditional branches and loops. Based on simple and clear, but powerful principles, the algorithm simultaneously minimizes the number of execution u... View full abstract»

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  • Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers

    Publication Year: 1989, Page(s):13 - 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (862 KB)

    This paper describes an efficient approach to sparse matrix factorization on vector supercomputers. The approach is suitable for application domains like circuit simulation that require the repeated direct solution of unsymmetric sparse linear systems of equations with identical zero-nonzero structure. An Overlap-Scatter data structure is used to represent the sparse matrix, enabling the use of mu... View full abstract»

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  • A Framework for Scheduling Multi-rate Circuit Simulation

    Publication Year: 1989, Page(s):19 - 24
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    This paper presents a theoretical framework for scheduling of subcircuit simulation in a multirate simulation environment. We show that event-driven simulation, selective-trace, and latency are subsumed by this framework. We assume that the circuit to be simulated is partitioned into subcircuits and that the dependency relations can be expressed as a directed acyclic graph. Each subcircuit predict... View full abstract»

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  • Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator

    Publication Year: 1989, Page(s):25 - 30
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    This paper presents several new methods for the efficient parallel simulation of VLSI circuits that contain feedback loops or "difficult" parts such as arrays, registers and pass-transistor networks. A new parallel algorithm has been developed for the efficient simulation of circuits containing feedback loops. It is based on dataflow scheduling and local relaxation of the loops. For the simulation... View full abstract»

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  • Template Style Considerations for Sea-of-Gates Layout Generation

    Publication Year: 1989, Page(s):31 - 36
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    SoGOLaR (Sea-of-Gates Optimized Layout and Routing) is program that generates functional cells for static CMOS circuits in the Sea-of-Gates layout style. Our generator is flexible and general enough to produce efficient layout for a wide variety of Sea-of-Gates template geometries. SoGOLaR has been used to make quantitative comparisons of several different templates with respect to area utilizatio... View full abstract»

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  • Gate Matrix Layout Synthesis with Two-Dimensional Folding

    Publication Year: 1989, Page(s):37 - 42
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (840 KB)

    We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal solution during the layout partitioning and... View full abstract»

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  • Transistor Size Optimization in the Tailor Layout System

    Publication Year: 1989, Page(s):43 - 48
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1081 KB)

    This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a spec... View full abstract»

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  • Tutorial/Panel Languages for Behavioral Description and Synthesis

    Publication Year: 1989, Page(s): 49
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (40 KB)

    This session begins with an introduction to the new behavioral design language standard under development in Japan. Following this half hour tutorial a discussion addresses the question of whether a single standard, such as VHDL, is sufficient for all tasks associated with the design, verification, and synthesis, of electronic systems. Each of the panelists will address the language standard activ... View full abstract»

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  • VLSI Design Language Standardization Effort in Japan

    Publication Year: 1989, Page(s):50 - 55
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (957 KB)

    This paper presents a new standard for a hardware design language (UDL/I: Unified Design Language for Integrated Circuit) that is being developed in Japan for application to logic synthesis technology. The features of UDL/I are as follows. It (1) is a logic synthesis oriented design language, (2) provides a formal and strict semantic definitions, (3) supports high-level constructs for easy hardwar... View full abstract»

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  • Experience with the ADAM Synthesis System

    Publication Year: 1989, Page(s):56 - 61
    Cited by:  Papers (43)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (661 KB)

    The ADAM synthesis system consists of two major subsystems: the program tools which synthesize RTL designs from behavioral descriptions and the prediction tools which guide the designer in exploring the design space for a good design. In this paper, we demonstrate the necessity for predictions in narrowing the search space. With the aid of an example, we describe the interaction of a designer with... View full abstract»

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  • Architectural Partitioning for System Level Design

    Publication Year: 1989, Page(s):62 - 67
    Cited by:  Papers (30)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1099 KB)

    Architectural partitioning is introduced as a new phase in system level synthesis. Architectural partitioning extracts high level structure from the behavior of an architecture. This paper describes the APARTY architectural partitioner, an automatic Architectural PARTYtioner that supports synthesis in the System Architect's Workbench. APARTY uses a unique multi-stage clustering technique. Knowledg... View full abstract»

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  • Integrated Scheduling and Binding : A Synthesis Approach for Design Space Exploration

    Publication Year: 1989, Page(s):68 - 74
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (642 KB)

    Synthesis of digital systems, involves a number of tasks ranging from scheduling to generating interconnections. The interrelationship between these tasks implies that good designs can only be generated by considering the overall impact of a design decision. The approach presented in this paper provides a framework for integrating scheduling decisions with binding decisions. The methodology suppor... View full abstract»

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