By Topic

Design Automation, 1987. 24th Conference on

Date June 28 1987-July 1 1987

Filter Results

Displaying Results 1 - 25 of 145
  • DAC '87 [Cover]

    Page(s): c1
    Save to Project icon | PDF file iconPDF (252 KB)  
    Freely Available from IEEE
  • DAC'87 Title Page

    Page(s): i
    Save to Project icon | PDF file iconPDF (48 KB)  
    Freely Available from IEEE
  • DAC'87 Copyright Page

    Page(s): ii
    Save to Project icon | PDF file iconPDF (62 KB)  
    Freely Available from IEEE
  • Executive Committee

    Page(s): iii
    Save to Project icon | PDF file iconPDF (146 KB)  
    Freely Available from IEEE
  • General Chairman's message

    Page(s): iv
    Save to Project icon | Request Permissions | PDF file iconPDF (68 KB)  
    Freely Available from IEEE
  • 1987 Program Committee

    Page(s): v
    Save to Project icon | PDF file iconPDF (41 KB)  
    Freely Available from IEEE
  • Awards pages

    Page(s): vi - vii
    Save to Project icon | PDF file iconPDF (125 KB)  
    Freely Available from IEEE
  • Call for papers

    Page(s): viii
    Save to Project icon | Request Permissions | PDF file iconPDF (71 KB)  
    Freely Available from IEEE
  • Advance Registration Form - 25th Design Automation Conference

    Page(s): ix
    Save to Project icon | PDF file iconPDF (78 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): xi - xx
    Save to Project icon | PDF file iconPDF (188 KB)  
    Freely Available from IEEE
  • Keynote Address: Emerging Imperatives for Engineers

    Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SSIM: A Software Levelized Compiled-Code Simulator

    Page(s): 2 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    This paper presents a new logic simulation technique that uses software levelized compiled-code (LCC) for synchronous designs. Three approaches are proposed: C source code, target machine code and interpreted code. The evaluation speed for the software LCC simulator (SSIM) is about 140,000 (gate) evaluations per second using C source code or target machine code, or 50,000 evaluations per second using interpreted code. It is about 40 to 100 times slower than the AIDA hardware LCC simulator, but is about one order of magnitude faster than a traditional software event simulator. For a 32-bit multiplier with gate activity more than 100%, experiments indicate that SSIM runs about 250 to 1,000 times faster than the AIDA event simulator that evaluates about 4,500 gates per second. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulator for MOS Circuits

    Page(s): 9 - 16
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator MOSSIM II. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Fast Signature Simulation Tool for Built-In Self-Testing Circuits

    Page(s): 17 - 25
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input and produces C code simulation modules comprising Boolean relations that represent the structure of the circuit. These C code modules are then compiled and linked together to form the basis of the compiled code simulator. Simulation is invoked by executing the compiled C code description of the circuit. The simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations Per Second (GEPS) have been achieved using the FSS. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Improved Systematic Method for Constructing Systolic Arrays from Algorithms

    Page(s): 26 - 34
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    An improved systematic method is introduced which reduces the number of ad hoc steps and provides all possible systolic solutions for a given algorithm. Algorithms are modeled using index space (geometric) representations where the index transformation matrices are determined systematically. Systolic arrays are produced by geometric projections. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Predicting Area-Time Tradeoffs for Pipelined Design

    Page(s): 35 - 41
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with the designs generated by an automated pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced Design Automation System of the University of Southern California. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

    Page(s): 42 - 49
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Automatic Rectilinear Partitioning Procedure for Standard Cells

    Page(s): 50 - 55
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&T Bell Laboratories LTX2 chip layout system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Standard Cell Placement Using Simulated Sintering

    Page(s): 56 - 59
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    Simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. In this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. In sintering one improves the quality of a processed material by heating it to a temperature close to the melting point. Analogously, we show that by starting out with a good initial configuration instead of a random configuration, and restricting uphill moves, we can considerably speed up simulated annealing. We use this idea for a standard cell placement program - GRIM in LTX2, an AT&T Bell Labs VLSI layout system. The initial configuration is produced either by changes to a layout the designer had done previously, or else by a fast program like min-cut. We obtain improvements of about 10% in chip area starting from a min-cut placement, in times about 3 times faster than our simulated annealing program (which itself is several times faster than other well known simulated annealing programs). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ESP: A New Standard Cell Placement Package Using Simulated Evolution

    Page(s): 60 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    ESP (Evolution-based Standard cell Placement) is a new program package designed to perform standard cell placement and includes macro-block placement capabilities. It uses the new heuristic method of simulating an evolutionary process in order to minimize the cell interconnection wire length. While achieving results comparable to or better than the popular Simulated Annealing algorithm, ESP performs its task about ten times faster. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Requirements for a Practical Software Engineering Environment

    Page(s): 67 - 73
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    This paper, primarily, presents the facilities that satisfy the user requirements for a modern software engineering environment under development on VS at Wang Laboratories, Inc. Requirements analysis is emphasized as a cornerstone for the future direction in building a practical product. Finally, based on user needs and trends, the environment is seen as providing the entire spectrum of software product life-cycle activities with an underlying active relational database. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Making of VIVID A Software Engineering Perspective

    Page(s): 74 - 81
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    This paper is about the software engineering facets of the making of a large programming systems product for symbolic VLSI CAD called VIVID. Issues such as how teams were organized, how conceptual integrity was maintained, and portability are discussed. Specific tools are also described that were built to aid in the development of VIVID. Methods are explored that aid in managing large systems with many directories and huge numbers of files. Finally, techniques for debugging such a large system are discussed. This paper's goal is to share these tools, techniques and methods to improve the software engineering practices used by all developers of CAD as well as other large software systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator

    Page(s): 82 - 88
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper formulates a comparative analysis to conventional layout design accounting for software development and maintenance. Critical factors in planning silicon compilation software development are identified. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Vector Hardware Accelerator with Circuit Simulation Emphasis

    Page(s): 89 - 94
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Hardware Switch Level Simulator for Large MOS Circuits

    Page(s): 95 - 100
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include hardware for simulating pass transistor circuits and for doing timing simulation. By using dynamic RAM for internal list storage, a single HSS processor can accommodate a circuit of up to 262,144 MOS devices. The HSS can be interfaced to a variety of host computers via a general purpose parallel interface, and in its current form offers a 25 times speed improvement compared to MOSSIM II running on a VAX 11-780. Timing mode offers similar speed advantages, with delay calculations that are sufficiently accurate for many simulation tasks. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.