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Design Automation, 1987. 24th Conference on

Date June 28 1987-July 1 1987

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Displaying Results 1 - 25 of 145
  • DAC '87 [Cover]

    Publication Year: 1987, Page(s): c1
    IEEE is not the copyright holder of this material | PDF file iconPDF (252 KB)
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  • DAC'87 Title Page

    Publication Year: 1987, Page(s): i
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  • DAC'87 Copyright Page

    Publication Year: 1987, Page(s): ii
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  • Executive Committee

    Publication Year: 1987, Page(s): iii
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  • General Chairman's message

    Publication Year: 1987, Page(s): iv
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  • 1987 Program Committee

    Publication Year: 1987, Page(s): v
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  • Awards pages

    Publication Year: 1987, Page(s):vi - vii
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  • Call for papers

    Publication Year: 1987, Page(s): viii
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  • Advance Registration Form - 25th Design Automation Conference

    Publication Year: 1987, Page(s): ix
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  • Table of contents

    Publication Year: 1987, Page(s):xi - xx
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  • Keynote Address: Emerging Imperatives for Engineers

    Publication Year: 1987, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • SSIM: A Software Levelized Compiled-Code Simulator

    Publication Year: 1987, Page(s):2 - 8
    Cited by:  Papers (34)  |  Patents (26)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (760 KB)

    This paper presents a new logic simulation technique that uses software levelized compiled-code (LCC) for synchronous designs. Three approaches are proposed: C source code, target machine code and interpreted code. The evaluation speed for the software LCC simulator (SSIM) is about 140,000 (gate) evaluations per second using C source code or target machine code, or 50,000 evaluations per second us... View full abstract»

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  • Simulator for MOS Circuits

    Publication Year: 1987, Page(s):9 - 16
    Cited by:  Papers (2)  |  Patents (17)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (880 KB)

    The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengt... View full abstract»

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  • A Fast Signature Simulation Tool for Built-In Self-Testing Circuits

    Publication Year: 1987, Page(s):17 - 25
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (875 KB)

    This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input... View full abstract»

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  • An Improved Systematic Method for Constructing Systolic Arrays from Algorithms

    Publication Year: 1987, Page(s):26 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (837 KB)

    An improved systematic method is introduced which reduces the number of ad hoc steps and provides all possible systolic solutions for a given algorithm. Algorithms are modeled using index space (geometric) representations where the index transformation matrices are determined systematically. Systolic arrays are produced by geometric projections. View full abstract»

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  • Predicting Area-Time Tradeoffs for Pipelined Design

    Publication Year: 1987, Page(s):35 - 41
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (709 KB)

    In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with the designs generated by an automated pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced Design Automation S... View full abstract»

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  • A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

    Publication Year: 1987, Page(s):42 - 49
    Cited by:  Papers (59)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1041 KB)

    An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from per... View full abstract»

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  • An Automatic Rectilinear Partitioning Procedure for Standard Cells

    Publication Year: 1987, Page(s):50 - 55
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&... View full abstract»

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  • Standard Cell Placement Using Simulated Sintering

    Publication Year: 1987, Page(s):56 - 59
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. In this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. In sintering one improves the quality of a processed material by heating it to a temperature close to the melting point. Analogously, we show that by starting out w... View full abstract»

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  • ESP: A New Standard Cell Placement Package Using Simulated Evolution

    Publication Year: 1987, Page(s):60 - 66
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (785 KB)

    ESP (Evolution-based Standard cell Placement) is a new program package designed to perform standard cell placement and includes macro-block placement capabilities. It uses the new heuristic method of simulating an evolutionary process in order to minimize the cell interconnection wire length. While achieving results comparable to or better than the popular Simulated Annealing algorithm, ESP perfor... View full abstract»

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  • Requirements for a Practical Software Engineering Environment

    Publication Year: 1987, Page(s):67 - 73
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    This paper, primarily, presents the facilities that satisfy the user requirements for a modern software engineering environment under development on VS at Wang Laboratories, Inc. Requirements analysis is emphasized as a cornerstone for the future direction in building a practical product. Finally, based on user needs and trends, the environment is seen as providing the entire spectrum of software ... View full abstract»

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  • The Making of VIVID A Software Engineering Perspective

    Publication Year: 1987, Page(s):74 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1037 KB)

    This paper is about the software engineering facets of the making of a large programming systems product for symbolic VLSI CAD called VIVID. Issues such as how teams were organized, how conceptual integrity was maintained, and portability are discussed. Specific tools are also described that were built to aid in the development of VIVID. Methods are explored that aid in managing large systems with... View full abstract»

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  • A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator

    Publication Year: 1987, Page(s):82 - 88
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (734 KB)

    Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper formulates a comparative analysis to conventional layout design accounting for software development and maintenance. Critical factors in planning silico... View full abstract»

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  • A Vector Hardware Accelerator with Circuit Simulation Emphasis

    Publication Year: 1987, Page(s):89 - 94
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (577 KB)

    A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstati... View full abstract»

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  • A Hardware Switch Level Simulator for Large MOS Circuits

    Publication Year: 1987, Page(s):95 - 100
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (666 KB)

    The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include hardware for simulating pass transistor circuits and for doing timing simulation. By using dynamic RAM for internal list storage, a single HSS proces... View full abstract»

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