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Design Automation, 1984. 21st Conference on

Date 25-27 June 1984

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Displaying Results 1 - 25 of 143
  • DAC '84 [Cover]

    Publication Year: 1984, Page(s): c1
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  • DAC'84 Title Page

    Publication Year: 1984, Page(s): i
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  • DAC'84 Copyright Page

    Publication Year: 1984, Page(s): ii
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  • Program at a glance

    Publication Year: 1984, Page(s): iii
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  • 1984 Design Automation Conference Committee

    Publication Year: 1984, Page(s): iv
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  • Chairman's Message

    Publication Year: 1984, Page(s): v
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  • Conference Keynote Speaker

    Publication Year: 1984, Page(s): vi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (115 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • 1984 Program Committee

    Publication Year: 1984, Page(s): vii
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  • Awards pages

    Publication Year: 1984, Page(s):viii - ix
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  • Call for papers

    Publication Year: 1984, Page(s): x
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  • Advance Registration Form - 22nd DAC

    Publication Year: 1984, Page(s): xi
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  • Hotel Registration Form - 22nd DAC

    Publication Year: 1984, Page(s): xii
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  • Table of contents

    Publication Year: 1984, Page(s):xiii - xx
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  • Opening remarks and keynote address

    Publication Year: 1984, Page(s): 1
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  • An Experimental MOS Fault Simulation Program CSASIM

    Publication Year: 1984, Page(s):2 - 9
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal evaluation is employed, based on the superposition of bidirectional static and dynamic signals. CSASIM also allows efficient simulation of many dif... View full abstract»

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  • The Second Generation MOTIS Mixed-Mode Simulator

    Publication Year: 1984, Page(s):10 - 17
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    This paper describes the second generation MOTIS mixed-mode simulator. In particular, It extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with local time-step control for timing simulation, and a switch level approach for unit delay simulation. It provides logic and timing verification for g... View full abstract»

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  • STAFAN: An Alternative to Fault Simulation

    Publication Year: 1984, Page(s):18 - 23
    Cited by:  Papers (53)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The c... View full abstract»

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  • THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator

    Publication Year: 1984, Page(s):24 - 31
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling t... View full abstract»

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  • A Wire Routing Scheme for Double-Layer Cell Arrays

    Publication Year: 1984, Page(s):32 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A channel model for routing double-layer cell arrays is presented. A switch-box is defined as an overlapping area of a horizontal channel and a vertical channel. Along the sides of switch-boxes, dynamic terminals are generated by the loose router and moved by the final router. A channel router, that is an extension of the "Dogleg Channel Router" introduced by D.N. Deutsch in 1976, is described. View full abstract»

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  • An Efficient Channel Router

    Publication Year: 1984, Page(s):38 - 44
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical "left edge algorithm". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorith... View full abstract»

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  • A Global Routing Algorithm for General Cells

    Publication Year: 1984, Page(s):45 - 51
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    An algorithm is presented which accomplishes the global routing for a building block or general cell routing problem. A line search technique is employed and therefore no grid is assumed either for the module placements or the pin locations. Instead of breaking the routing surface up into channels, a maze search finds acceptable global routes while avoiding the blocks. Both multi-pin terminals and... View full abstract»

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  • A Symbolic-Interconnect Router for Custom IC Design

    Publication Year: 1984, Page(s):52 - 58
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router ... View full abstract»

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  • HARPA: A Hierarchical Multi-Level Hardware Description Language

    Publication Year: 1984, Page(s):59 - 65
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    In this paper, a new hardware description language -HARPA- is presented which was specially designed to permit the description of hierarchically structured digital systems at different levels of abstraction. The system building modules can be represented in terms of their structure, their behavior or a combination of both, as appropriate. A set of data types is provided which is adequate to charac... View full abstract»

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  • ADL: An Algorithmic Design Language for Integrated Circuit Synthesis

    Publication Year: 1984, Page(s):66 - 72
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    The Algorithmic Design Language (ADL), provides a means to procedurally describe the functional, circuit, schematic and mask aspects of integrated circuits. The constructs of this language have been coded in the C language and are intended for application to IC design. C programs that incorporate ADL routines are executed to build a data base from which CIF files, input files to circuit simulation... View full abstract»

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  • A Symbolic Functional Description Language

    Publication Year: 1984, Page(s):73 - 80
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable fo... View full abstract»

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