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Design Automation, 1982. 19th Conference on

Date 14-16 June 1982

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Displaying Results 1 - 25 of 142
  • DAC'82 Title page

    Page(s): i
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  • DAC'82 Copyright Page

    Page(s): ii
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  • DAC'82 Program Page

    Page(s): iii
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  • Call for papers

    Page(s): iv
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  • 1982 Design Automation Conference Committee

    Page(s): v
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    Freely Available from IEEE
  • 1982 DA Conference Program Committee

    Page(s): vi
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  • Chairman's Message

    Page(s): vii
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  • Conference Keynote Speaker

    Page(s): viii
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    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Table of contents

    Page(s): ix - xvi
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  • ROBOTICS: The New Automation Tool

    Page(s): 2 - 8
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    Industrial robots have seen limited use by industries for over a decade but until the auto industry introduced robotics for spot welding applications in the late 60s the robot was not considered seriously. Now they are readily accepted throughout industry. The reasons for their current popularity are the rapidly increasing costs of labor and the seemingly declining productivity of todays workers. In addition, robots today are credited for additional product and quality improvements not seriously considered in the past. Benefits similar to those that have long been attributes associated with hard automation. This paper looks at robotics from a users viewpoint and addresses some of the benefits and concerns attributable to their use. To this end, this paper will describe several applications that are currently used in production with results relative to production gains, side benefits and operator acceptance. View full abstract»

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  • Design for Testability

    Page(s): 9
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    This presentation will discuss the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs. These techniques include the three main areas of Design for Testability, 1) Ad Hoc approaches; 2) Structured approaches; and, 3) Self Test/Built-in Test approaches. View full abstract»

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  • A Retrospective on Software Engineering in Design Automation

    Page(s): 10 - 14
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    We have observed the effect that software engineering can have on design automation throughout the four years of the Designer's Workbench (DWB) project. DWB is a design aids delivery system that interfaces the user to a variety of applications programs. This paper describes our experience in using various techniques and our conclusions about their value. The improvements that occurred in the second design iteration illustrate the effect of using a consistent methodology. The introduction of table-driven, finite state machines and software utilities provided an unusually adaptable and flexible environment for adding new applications. The resultant design aids delivery system is able to respond to the rapid changes that occur in the supported technologies and provide tools when needed rather than after the customers have completed their project. View full abstract»

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  • Designer's Workbench: Delivery of CAD Tools

    Page(s): 15 - 22
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    Designer's Workbench (DWB) is a systematic approach to design aids integration that overcomes most of the barriers that frequently restrict the use of those aids. In combination with the UNIX (FOOTNOTE: UNIX is a trademark of Bell Laboratories.) operating system [1][2], DWB manages both the flow and the form of data that is required by application programs that reside on various computer systems. The techniques described in this paper enable the Designer's Workbench development team to respond quickly to electrical and physical designers' needs. Because of this ability to respond quickly to users' needs Designer's Workbench has had uncommon growth and acceptance in the user community. View full abstract»

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  • A Utilitarian Approach to CAD

    Page(s): 23 - 29
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    The benefits of using and writing software utilities are appreciated by most software engineers. However, many Computer-Aided Design (CAD) systems do not take full advantage of this technology. This could be because good utilities do not exist, because CAD developers are not aware of existing utilities, or because developers do not know what features to include and leave out when they are writing their own utilities. As with much of computer science, the art of effectively using and writing software utilities has remained just that: an art. This paper discusses the desirable features of good software utilities for CAD and describes techniques that encourage effective use of existing utilities as well as the specification and implementation of new ones. Throughout the paper, experiences from a four year development effort in Designer's Workbench (DWB) [1] are used as examples (both good and bad). View full abstract»

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  • An Analytical Method for Compacting Routing Area in Integrated Circuits

    Page(s): 30 - 37
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    An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed. View full abstract»

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  • Optimal Single Row Router

    Page(s): 38 - 45
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    The single row approach represents a systematic suboptimal approach to the general multilayer rectilinear wire routing problem. With this approach, the single row wiring problem (i.e., one where all the points are collinear) forms the backbone of the general multilayer wiring problem. We consider the problem of generating minimum width layouts for single row wiring problems. Our algorithm, which is not grid-based, is enumerative and uses a strong bounding criterion. View full abstract»

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  • A New Two-Dimensional Routing Algorithm

    Page(s): 46 - 50
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    A new heuristic algorithm for two-dimensional routing utilizing two distinct layers is described. It is assumed that all terminals are on the boundary of a rectilinear routing region with or without cutout sections. Terminals on vertical boundary segments are assumed to be on one layer and those on horizontal boundary segments are on the other layer. This algorithm finds all possible paths with minimum corners for a net and then chooses one of those paths by considering path length, the likelihood of blocking nets not yet routed, the usage of vacant tracks, and the necessity of going through an area expected to be congested. A dynamic data structure is maintained. If h and v are the numbers of horizontal and vertical tracks, n is the number of nets, and t is the number of terminals, then the storage requirement is o(hv) and the time complexity is o((t-n)hv). For h=23, v=64, n=47, and t=130 the storage required is 60K bytes and cpu time is 16 seconds. This algorithm is implemented in the C language on a VAX 11/780 under the Berkeley Unix (FOOTNOTE: Unix is a trademark of Bell Laboratories.) Operating system, as part of the LTX layout system of the layout aids group at Bell Laboratories, Murray Hill. View full abstract»

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  • The Yorktown Simulation Engine: Introduction

    Page(s): 51 - 54
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    The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. This paper introduces the YSE and describes its top-level architecture. View full abstract»

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  • The Yorktown Simulation Engine

    Page(s): 55 - 59
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    The Yorktown Simulation Engine (YSE) is a high speed special purpose parallel processor designed and built at the I.B.M. Thomas J. Watson Research Center to simulate the logical operation of large digital networks. A full YSE configuration simulates networks of up to 2,000,000 gates at a rate exceeding 3 billion gate computations per second, doing more simulation in just eight hours than an IBM 370/168 does in an entire year. This paper reviews gate-level logic simulation and describes the architecture and hardware implementation of the YSE. A companion paper by G. Pfister and E. Kronstadt discusses the YSE software. View full abstract»

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  • Software Support for the Yorktown Simulation Engine

    Page(s): 60 - 64
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    The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. This paper describes the software support for the YSE. View full abstract»

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  • A Logic Simulation Machine

    Page(s): 65 - 73
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    Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved. View full abstract»

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  • IBM 3081 System Overview and Technology

    Page(s): 75 - 82
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    The development of the IBM 3081 established the methodology for designinc and manufacturing a high-performance computer from an LSI chip technology. The high density packaging of the LSI chip is used to minimize interconnections and to support a fast machine cycle time. This paper will describe the methods used and will highlight some of the design problems that were solved, to offer an understanding of the challenges that LSI brings to the design cycle. View full abstract»

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  • Design Verification System for Large-Scale LSI Designs

    Page(s): 83 - 90
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    This paper describes the changing environment of large-scale computer designs as they are influenced by the advance of technology. This changing environment makes it necessary for design verification to be part of the basic design cycle. The design verification methodology presented in this paper represents a minimum scheduled savings of 75% for an LSI machine as compared to any conventional type of design system. It allows the computer industry to design timely systems in the range of one-million circuits and to design them with a cost-effective design system. In addition to savings in schedule, the system described guarantees a high quality design with minimum impact on customer satisfaction because of design errors. The range of effectiveness that can be obtained on a product using this methodology is from 85-95% effective. View full abstract»

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