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June 29 1981-July 1 1981

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Displaying Results 1 - 25 of 146
  • DAC'81 [Cover]

    Publication Year: 1981, Page(s): c1
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    Freely Available from IEEE
  • DAC'81 Title Page

    Publication Year: 1981, Page(s): i
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  • DAC'81 Copyright Page

    Publication Year: 1981, Page(s): ii
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  • DAC'81 Conference Committee

    Publication Year: 1981, Page(s): iii
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  • DAC'81 Program Committee

    Publication Year: 1981, Page(s): iv
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  • Call for papers

    Publication Year: 1981, Page(s): v
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  • Table of contents

    Publication Year: 1981, Page(s):vii - xvii
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  • 18th DAC At A Glance

    Publication Year: 1981, Page(s): xviii
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  • Chairman's message

    Publication Year: 1981, Page(s): 1
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  • Keynote speaker

    Publication Year: 1981, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • CAD for Military Systems, An Essential Link to LSI, VLSI and VHSIC Technology

    Publication Year: 1981, Page(s):3 - 12
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    Government involvement in the development of computer aided design (CAD) tools for electronic circuits has a long history. The advent of large scale integrated (LSI) circuits, going into the 1970's, pulsed the development of the "standard cell" and "gate array" design methodologies and supporting CAD. Despite these burgeoning technologies, little custom LSI technology found its way into military s... View full abstract»

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  • Recent Developments in Representation in the Science of Design

    Publication Year: 1981, Page(s):13 - 21
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A recent goal in computer aided design is the representation of a design artifact in a form sufficient to support all analyses and to determine that the design is realizable. Some aspects of a theory of design representations are presented. Benefits of developing such a theory is discussed. View full abstract»

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  • The Hughes Automated Layout System - Automated LSI/VLSI Layout Based on Channel Routing

    Publication Year: 1981, Page(s):22 - 28
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The Hughes Automated Layout System (HAL) is intended to provide fast, accurate, and efficient layout of LSI/VLSI circuits. The HAL development plan calls for an evolutionary development in three phases, with each phase providing a usable design system. HAL(I) is limited to standard cell layout and is now operational. HAL(II), which will permit more complex geometries, and HAL(III), which will add ... View full abstract»

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  • An Algorithm for Searching Shortest Path by Propagating Wave Fronts in Four Quadrants

    Publication Year: 1981, Page(s):29 - 36
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper discusses a new algorithm for searching the shortest path in VLSIs by propagating wave fronts in four quadrants. The algorithm has been experimentally programmed in FORTRAN IV on a Hitac M-200H computer. The main advantages of this algorithm are: 1. When there is a shortest path between two points, it can always be found by this algorithm; 2. In this algorithm, searching waves are divid... View full abstract»

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  • Computation of Power Supply Nets in VLSI Layout

    Publication Year: 1981, Page(s):37 - 42
    Cited by:  Papers (17)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    For a given placement of macrocells with given power consumption a full automatic layout of power supply and ground nets has been developped. The varying width in different segments of these nets is calculated from local current values resulting in rectangles presenting the net segments. These rectangles are embedded in the routing plane with regard to given design rules. View full abstract»

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  • Design Automation Status in Japan

    Publication Year: 1981, Page(s):43 - 50
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper surveys the Japanese design automation (DA) status and activities. First, the DA statistics for major Japanese organizations are presented. These statistics show the status of logic, physical and test DA for digital systems and LSIs. Second, notable DA activities of Japanese manufacturers, laboratories and universities are introduced. View full abstract»

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  • A Design Automation System for Electronic Switching Systems

    Publication Year: 1981, Page(s):51 - 58
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    This paper describes the development and operation experience of NTT's design automation (DA) system for analog/digital switching systems. The DA system is composed of several subsystems, such as logic design, physical design, documentation and manufacturing data conversion programs, organized around the centralized data base management system. By using this system, hardware standardization and pr... View full abstract»

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  • An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

    Publication Year: 1981, Page(s):59 - 65
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automaic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures. View full abstract»

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  • Creating and Updating Space Occupancy and Building Plans using Interactive Graphics

    Publication Year: 1981, Page(s):66 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Interactive graphics systems have been used for generating integrated circuit and printed circuit layouts. Now these systems are being used to create building plans as well. This paper discusses the mechanization of "rent plans" (a set of plans which shows how building space is occupied), its background, several applications, and possible future developments. View full abstract»

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  • Plant Design Management System (PDMS) in Action

    Publication Year: 1981, Page(s): 74
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    First Page of the Article
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  • Interactive Shape Generation and Spatial Conflict Testing

    Publication Year: 1981, Page(s):75 - 81
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A general purpose, research oriented, interactive modeling system is presented. It is based on two different coherent polyhedral shape representations: a planar graph, used for computation and data manipulation, and a relational-database for compact store and general communication with application programs. The two representations effectively partition the system shape-space into active and inacti... View full abstract»

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  • Symbolic Simulation for Functional Verification with ADLIB and SDL

    Publication Year: 1981, Page(s):82 - 89
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence of different levels of abstraction and asynchronous timing. This paper motivates interest in this problem and provides background information on ver... View full abstract»

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  • On Proving the Correctness of Optimizing Transformations in a Digital Design Automation System

    Publication Year: 1981, Page(s):90 - 97
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    As part of our research for the Carnegie-Mellon University Design Automation System, we have been investigating methods for proving that the system produces correct designs from correct specifications. This paper presents a mathematical model of the behavior of hardware descriptions which has been used to prove that some of the optimizing transformations applied to abstract hardware descriptions i... View full abstract»

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  • Deterministic Systems Design from Functional Specifications

    Publication Year: 1981, Page(s):98 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The approach presented is intended to help solve design problems above the logical level. It is based on the use of a special class of PETRI nets to model system components and data flows. Instead of describing an already existing design the functions to be implemented are introduced by a specification program. This serves as a basis for algorithms generating a controlled system structure which ex... View full abstract»

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  • Hierarchical Design Verification for Large Digital Systems

    Publication Year: 1981, Page(s):105 - 112
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    This paper describes a hierarchical design verification system, consisting of a logic verification subsystem, MIXS(1), a timing verification subsystem, NELTAS(2), and a hierarchical data base. MIXS is a mixed level simulator, which can handle both functional and chip or gate level models with a unified simulation mechanism based on "node" model concept. NELTAS analizes delay time by tracing logica... View full abstract»

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