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VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

Date 3-7 Jan. 2006

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  • 19th International Conference on VLSI Design - Cover

    Publication Year: 2006 , Page(s): c1
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  • Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

    Publication Year: 2006
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  • 19th International Conference on VLSI Design - Copyright Page

    Publication Year: 2006 , Page(s): iv
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  • 19th International Conference on VLSI Design - Table of contents

    Publication Year: 2006 , Page(s): v - xv
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  • Message from the General Chairs

    Publication Year: 2006 , Page(s): xvi - xviii
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  • Message from the Program Chairs

    Publication Year: 2006 , Page(s): xix - xxi
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  • Message from the Organizing Chair

    Publication Year: 2006 , Page(s): xxii - xxiii
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  • Conference Committee

    Publication Year: 2006 , Page(s): xxiv - xxvi
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  • Program Committee

    Publication Year: 2006 , Page(s): xxvii - xxviii
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  • Organizing Committee

    Publication Year: 2006 , Page(s): xxix - xxx
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  • VLSI Design 2005 Conference Awards

    Publication Year: 2006 , Page(s): xxxi - xxxii
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  • VLSI Design 2006 Conference Awards

    Publication Year: 2006 , Page(s): xxxiii
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  • list-reviewer

    Publication Year: 2006 , Page(s): xxxiv - xxxvii
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  • VLSI Design 2006 Conference Awards

    Publication Year: 2006 , Page(s): xxxviii
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  • Embedded Systems Design Conference History

    Publication Year: 2006 , Page(s): xxxix
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  • Call for Participation: VLSI Design 2007

    Publication Year: 2006 , Page(s): xl
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  • Call for Participation: 10th IEEE VLSI Design & Test Symposium

    Publication Year: 2006 , Page(s): xli
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  • Low-power design strategies for mobile computing

    Publication Year: 2006
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (77 KB) |  | HTML iconHTML  

    Summary form only for tutorial. The advent of nanometer design process has enabled the integration of multi-million gates with a variety of functionality as a system-on-chip (SoC). The demand for high levels of integration in SoCs are fueled by a strong demand in consumer oriented products for hand held computing, multimedia and other communication products. For these products, power budget is a very critical factor deciding the battery life, size and weight of the portable devices. Designers need to use energy reduction techniques to support as many design features and functions and still keep within the system power budget. The tutorial presents a comprehensive introduction to low power design techniques, and challenges in various facets of the design process. We present an in-depth introduction to concepts with a holistic view to overcome the various challenges and present strategies with a practical approach to the key issues in the design of low power solutions. All the techniques are discussed with practical examples. View full abstract»

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  • Technology impacts on sub-90nm CMOS circuit design & design methodologies

    Publication Year: 2006
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB) |  | HTML iconHTML  

    Summary form only for tutorial. This tutorial discusses design challenges of scaled CMOS circuits in sub-90nm technologies and the design methodologies required to design them in order to produce robust designs with desired power performance trade-off. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines. On the technology front, the question arises whether we can continue along the traditional CMOS scaling path - reduce effective oxide thickness, improve channel mobility, and minimize parasitics. On the design front, researchers are exploring various circuit design techniques to deal with process variation, leakage and soft errors. View full abstract»

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  • Beyond RTL: advanced digital system design

    Publication Year: 2006
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    Summary form only for tutorial. This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex IP blocks and high-speed buses and interconnection networks. This tutorial addresses the following emerging challenges: architectural exploration, HW/SW co-design, complex control and concurrency, correctness and verification, timing closure, and low-power. The tutorial focuses on language facilities and synthesis techniques that dramatically simplify and shorten the process of correct chip design by raising the level of abstraction on multiple dimensions without sacrificing final hardware quality. View full abstract»

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  • System aspects of analog to digital converter designs

    Publication Year: 2006
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    Summary form only for tutorial. In this section, the principles of operation of data-converters, the different architectures, and the important specification parameters are presented. We begin by discussing the fundamental processes of analog-digital conversion: quantization, sampling, resolution. The various figures-of-merit of an ADC such as integral nonlinearity (INL), differential nonlinearity (DNL) and signal-noise ratio (SNR) are then presented. In the second part of this section, a classification of well-known A/D converter architectures is presented. The advantages and disadvantages of each of these architectures, their respective resolution-speed-power consumption ranges, and the applications in which they find use are discussed. View full abstract»

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  • Interconnect process variations: theory and practice

    Publication Year: 2006
    Cited by:  Papers (1)
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    Summary form only for tutorial. Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics. Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Foundations for statistical parasitic extraction and results from correlation to silicon are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered. View full abstract»

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  • Design challenges for high performance nanotechnology

    Publication Year: 2006
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    Summary form only for tutorial. This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nanotechnology. The focus is on design challenges that are experienced in microprocessor designs. It captures the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification. It describes the requirements to meet power, timing, physical dimension and process portability goals with nanotechnology. It also addresses the pre and post silicon verification difficulties that have a direct impact on taking the product to market. View full abstract»

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  • DFM, DFT, silicon debug and diagnosis -the loop to ensure product yield

    Publication Year: 2006
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    Summary form only for tutorial. After an introduction of the issues involved in the first section, the second section covers design-for-manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered. View full abstract»

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  • A comprehensive SoC design methodology for nanometer design challenges

    Publication Year: 2006
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (87 KB) |  | HTML iconHTML  

    Summary form only for tutorial. SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed. View full abstract»

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