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Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on

Date 17-19 Jan. 2006

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  • Third IEEE International Workshop on Electronic Design, Test and Applications

    Page(s): c1
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  • Third IEEE International Workshop on Electronic Design, Test and Applications - Title Page

    Page(s): i - iii
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  • Third IEEE International Workshop on Electronic Design, Test and Applications - Copyright

    Page(s): iv
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  • Third IEEE International Workshop on Electronic Design, Test and Applications - Table of contents

    Page(s): v - xi
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  • Message from the General Chairs

    Page(s): xii
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  • Message from the Program Chairs

    Page(s): xiii
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  • Committees

    Page(s): xiv
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  • list-reviewer

    Page(s): xvi
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  • Some common aspects of design validation, debug and diagnosis

    Page(s): 6 pp. - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    Design, verification and test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping View full abstract»

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  • Using dither to improve the performance of lossy sigma-delta modulators

    Page(s): 6 pp. - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (350 KB) |  | HTML iconHTML  

    Conventional sigma-delta (SigmaDelta) analog-to-digital (AD) converters are based on an active analog SigmaDelta modulator followed by a digital filter. In earlier papers we proposed a new architecture for a first-order SigmaDelta modulator that needs no active analog components. Its advantage is that AD converters can be implemented within FPGAs or directly in the software of microprocessors. Its disadvantage is, however, that it realizes a lossy SigmaDelta modulator with an accompanying limited resolution. Here we propose to use dither-injection to relax that resolution limitation and we present simulation results showing that our ideas work View full abstract»

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  • CMOS Schottky diode microwave power detector fabrication, SPICE modeling, and applications

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    CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35μ CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schottky diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits and a low-voltage reference circuit. View full abstract»

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  • Design and implementation of analog multitone signal generator using regenerative frequency divider for OFDM transceiver

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    This paper is concerned with design and an integrated circuit implementation of a multicarrier quadrature phase generator for application in analog spectral synthesis and orthogonal frequency division multiplexing transceiver using amplitude phase shift keying using 0.18μ technology. A noble analog or sampled data based rotational quadrature oscillator has been designed for generating quadrature signals. Scheme of multicarrier generation studied includes multiple frequency generation, using regenerative frequency dividers and mixers. Simulation results and performance of multicarrier generation have been presented. This scheme shows very low power consumption than typical method of multi-frequency signal synthesis using IFFT. View full abstract»

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  • Image noise removal in Nakagami fading channels via Bayesian estimator

    Page(s): 4 pp. - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (565 KB) |  | HTML iconHTML  

    A maximum likelihood for Bayesian estimator based on alpha-stable was discussed in our previous papers. It is in terms of closer to a realistic situation, and unlike previous methods used for Bayesian estimator, for the case discussed here it is not necessary to know the variance of the noise. The Bayesian estimator here is based on in a Nakagami fading channel. Our previous research results has been extended to that Bayesian estimator that we investigated is still working well for the image noise removal in Nakagami fading channels. As an example, an improved Bayesian estimator (soft and hard threshold methods), is illustrated in our discussion View full abstract»

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  • A hybrid scheme for temporal video segmentation

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    Video temporal segmentation is normally the first and important step for content-based video applications. Although existing research on shot cut detection is active and extensive, it still remains a challenge to achieve accurate detection of all types of shot boundaries. In this paper, we propose a hybrid scheme to combine some features and techniques for detecting all sorts of shot cuts inside general videos. The hybrid scheme contains two processing modes, which are unified by a mode-selector to decide which mode the scheme should work on in order to achieve accurate temporal video segmentation. Via using the publicly test data set from Carleton University, we report extensive experimental results to evaluate the proposed algorithm. In comparison with existing algorithms, the experimental results support that the proposed algorithm outperforms the benchmark in terms of the precision-recall rates in detecting all types of shot cuts. View full abstract»

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  • Hardware implementation for face detection on Xilinx Virtex-II FPGA using the reversible component transformation colour space

    Page(s): 6 pp. - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (469 KB) |  | HTML iconHTML  

    Face detection is the process of locating the position where faces are present in an image. Not all proposed face detection methods are suitable for direct hardware implementation. This paper explains a method that utilises the reversible component transformation (RCT) colour space and outlines its transition from a software- to hardware-based implementation. The hardware performance and efficiency of the RCT algorithm is examined using the Xilinx Virtex-II field programmable gate arrays (FPGA). Results show that there is almost negligible difference in performance after transition to hardware and its implementation on FPGA requires 255,416 NAND gates, which is only slightly more than twice the number of NAND gates of a basic video-in application View full abstract»

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  • Using design patterns to overcome image processing constraints on FPGAs

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the algorithm. To aid in the process this paper details the application of design patterns to image processing algorithm development. Design patterns embody experience and through reuse provide tools for solving particular mapping problems. The effectiveness of design patterns for overcoming constraints in the mapping process is illustrated in the context of a real world example that focuses on the development of a real-time object tracking algorithm implemented on an FPGA. View full abstract»

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  • A low cost, high quality embedded array DFT technique for high performance processors

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by ∼50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel® high performance microprocessor design. View full abstract»

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  • VertiCal, a universal calibration system for eSys high performance 32-bit PowerPC microcontrollers; test challenges & solution

    Page(s): 4 pp. - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    VertiCal is a calibration system for eSys, a family of 32-bit automotive microcontrollers based on the PowerPC architecture. To utilize the calibration system, a common scale package among the derivatives is required and a table of universal pin locations including the calibration pins is properly defined. However, the inclusion of the calibration pins has induced an uncommon structure where two balls in the package are sharing a pad on the die. This structure has created some test challenges. This paper discusses in detail the problem, followed by approaches in analysis and experimental results View full abstract»

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  • Enabling test-time optimized pseudorandom bit stream (PRBS) 231 BER testing on automated test equipment for 10Gbps device

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    Pseudorandom bit stream (PRBS) testing is critical in network and communication devices to ensure compliant to industry standards. Thus, many new high speed devices have been designed with internal PRBS generator and comparator capability for built-in-self-test. On the other hand, devices that are without this design-for-test feature will have to be tested through conventional methods such as bit error rate (BER) tester due to capability limitation on automated test equipment (ATE). However, this setup is typically expensive and unfriendly in a high volume manufacturing due to long test time, rack and stack setup and dedicated systems. A novel idea was conceived where a pair of programmable PRBS drivers and comparators is embedded into the test loadboard to provide the BER test capability. Coupled with an intelligent BER algorithm, the solution provides a low cost BER test solution that can be implemented in a high volume manufacturing using only a mixed signal ATE. View full abstract»

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  • Test cost saving and challenges in the implementation of ×6 and ×8 parallel testing on freescale 16-bit HCS12 microcontroller product family

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    One of the pressing issues faced by the semiconductor industry today is the cost of testing, especially on the low cost and high volume microcontroller (MCU) supply to automotive market. This paper describes the general consideration and justification made on the investment of tester, handler and device interface board (DIB) to enable the ×6 and ×8 multi-site testing on the 80 and 112pin counts 16-bit HCS12 MCU in quad flat pack (QFP) package and the associate test cost reduction and tester saving estimation. Test issue encounter on the first spin of ×6 and ×8 DIB and how it was resolved through re-design of the DIB also is presented. This finding also provide the PCS designer the valuable information on the constraint of trace length and component layout one need to take into consideration when design a multi-site DIB use for high speed MCU testing to avoid AC or DC test failure induced by excessive capacitive loading and resistance drop over signal trace on the DIB. View full abstract»

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  • Design of high-speed metal-semiconductor-metal photodetectors: an optimization-based approach

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    The finger sizing of interdigitated Schottky-barrier metal-semiconductor-metal photodetectors (MSM-PD) is discussed in this paper. We observe that a MSM-PD geometry with fast response speed can be determined by solving a special form of optimization problem called posynomial programming, for which very efficient global optimization methods have been developed. Our method, therefore, yields completely automated finger sizing of MSM-PD, directly from specifications. View full abstract»

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  • Dual-head marking performance optimisation via evolutionary solutions

    Page(s): 4 pp. - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    This paper presents a new approach to optimise the performance of a multi-head marking system in terms of its marking speed. This processing method named as MMA (molecular marking optimisation algorithm) adopts the use of genetic algorithm. The advantage of the 'self evolving' nature of the genetic algorithm has been considered to discover the most relevant combination of features for each diagnosis considered. The knowledge acquired by the process is interpreted and mapped into vectors, which are kept in the database and used by the system to guide its reasoning process. The representation approach has been implemented via computer program in order to achieve optimised marking performance. Also, the performance of the new operators for evolutionary approaches to the time-based problem has been discussed in the paper View full abstract»

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  • Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed. View full abstract»

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  • Curvature compensated CMOS bandgap with sub 1V supply

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    We describe a bandgap circuit capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18μm CMOS technology and operates with 0.9 V supply voltage, consuming 5μA current. The circuit achieves 7ppmρK of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60° centigrade. View full abstract»

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  • Energy efficient cache timing with performance bound

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    Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed. View full abstract»

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