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High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International

Date Nov. 30 2005-Dec. 2 2005

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Displaying Results 1 - 25 of 47
  • Tenth Annual IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No. 05TH8856)

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  • Copyright page

    Page(s): ii
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  • Chairs' welcome message

    Page(s): iii
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  • Committees

    Page(s): iv
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  • Table of contents

    Page(s): v - viii
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  • [Breaker page]

    Page(s): 1 - 2
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  • Simulation-based functional test generation for embedded processors

    Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key to develop a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the growth in design size. This work proposes a functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions. One is called Boolean learning to be applied on random logic and the other is called arithmetic learning to be applied on datapath modules. We demonstrate the effectivenesses and discuss the limitations of these techniques through experiments on benchmark circuits. We validate the overall test generation methodology based on the OpenRISC 1200 microprocessor. View full abstract»

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  • Scalable defect mapping and configuration of memory-based nanofabrics

    Page(s): 11 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The idea is to start by obtaining a defect map of the target nanofabric, and then configure the desired functionality 'around' its defective components. In this paper, we argue for the suitability of memory-based computing nanofabrics, address the level of granularity at which defect mapping and configuration should be performed on such fabrics, and discuss the role of hierarchy towards controlling complexity. We then propose a group testing method to enable self-testing and self-configuration for appropriately architected memory-based nanofabrics. The proposed testing method is scalable and simple, in that it enables the entire fabric to be tested and configured using a relatively small number of easily configurable triple-module-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Our experimental results demonstrate the effectiveness of the proposed method for a representative set of benchmark kernels. View full abstract»

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  • Improvement of fault injection techniques based on VHDL code modification

    Page(s): 19 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    Fault injection techniques based on the use of VHDL as design language offer important advantages with regard to other fault injection techniques. First, as they can be applied during the design phase of the system, they allow reducing the time-to-market. Second, this type of techniques presents high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high capability of fault modeling. However, it is difficult to implement automatically these techniques in a fault injection tool, mainly the insertion of saboteurs and the generation of mutants. In this paper, we present new models of saboteurs and mutants that can be easily applicable in VFIT, a fault injection tool developed by the Fault-Tolerant Systems Research Group (GSTF) of the Technical University of Valencia. View full abstract»

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  • MVP: a mutation-based validation paradigm

    Page(s): 27 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    A mutation-based validation paradigm that can handle complete high-level microprocessor implementations is presented. First, a control-based coverage measure is presented that is aimed at exposing design errors that incorrectly set control signal values. A method of automatically generating a complete set of modeled errors from this coverage metric is presented such that the instantiated modeled errors harness the rules of cause-and-effect that define mutation-based error models. Finally, we introduce an automatic test pattern generation technique for high-level hardware descriptions that solves multiple concurrent constraints and is empowered by concurrent programming. View full abstract»

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  • [Breaker page]

    Page(s): 35 - 36
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  • Establishing latch correspondence for embedded circuits of PowerPC microprocessors

    Page(s): 37 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB) |  | HTML iconHTML  

    We present a latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondences for latches (potentially nonscanable) in complex state machines having cyclic dependencies. Our methodology not only answers latch correspondence, but also provides polarity of the correspondence. This is a major advantage over earlier latch mapping algorithms. Experimental results obtained on embedded circuits from live PowerPCreg design projects have shown that our technique fares better than a leading vendor tool in mapping latches - in both quantitative (more latches mapped) and performance (time/memory used) aspects View full abstract»

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  • Sequential equivalence checking based on k-th invariants and circuit SAT solving

    Page(s): 45 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (146 KB) |  | HTML iconHTML  

    In this paper, we first present the concept of the k-th invariant. In contrast to the traditional invariants that hold for all cycles, k-th invariants guarantee to hold only after the k-th cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to compute the k-th invariants, and are further integrated with a sequential SAT solver for checking sequential equivalence. Experimental results demonstrate that the sequential equivalence checking framework can efficiently verify large industrial designs. View full abstract»

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  • VERISEC: verifying equivalence of sequential circuits using SAT

    Page(s): 52 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    In this paper we propose a framework to verify equivalence of sequential circuits using Boolean satisfiability (SAT). We tackle a problem that is harder than the traditional sequential hardware equivalence; specifically, we address the uninvestigated problem of verifying delay replaceability as stated in V. Singhal et al. (2001) of two sequential designs. This notion of sequential equivalence does not make any assumptions either about the design-environment or about the design's steady state behavior. Thus, verifying delay replaceability is considered as hard as verifying safe replaceability according to V. Singhal et al. (2001) of sequential circuits (conjectured as EXPSPACE complete). Our SAT-based framework has the following salient features: (a) a methodology to inductively prove equivalence (delay replaceability) of sequential circuits with no assumptions about any initial state; (b) a scheme to include sequential logic implications into the framework; and (c) a low-cost scheme to identify equivalent flip-flop pairs on the fly. We used our tool to successfully verify several sequential benchmark circuits. Low execution times make our framework practical and scalable. View full abstract»

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  • [Breaker page]

    Page(s): 60 - 62
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  • Automated clock inference for stream function-based system level specifications

    Page(s): 63 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB) |  | HTML iconHTML  

    Among system-level design frameworks and languages, system modeling approaches based on functional programming aim at rapid specification and prototyping of processing of data streams. Models constructed with functional programs provide highly modular and computationally correct models for prototyping and simulation purposes. For design space exploration, the functional programming frameworks provide semantically sound methodologies for establishing formal refinement relations and secure a trustable design automation flow. However, the stream computations expressed by functions embody an implicitly single clocked model of computation (untimed or fully synchronous) which does not take advantage of possible polychronous (multiclock) computation inherent to the system's dataflow. To this end, we propose a type inference system for representing a synchronous and multiclocked model of computation in the typed and functional programming language ML. Along the way, we address the issue of performing the automated refinement of implicitly timed stream functions in a model of computation that supports reasoning on partially ordered signal clocks, allowing for formal design transformation and verification to be performed in the context of a functional programming environment. View full abstract»

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  • Cosimulation of ITRON-based embedded software with SystemC

    Page(s): 71 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    This paper presents an RTOS-centric timed cosimulation with SystemC for embedded system design. In our cosimulation environment, a SystemC simulator and an RTOS kernel model are communicated and synchronized with each other. Our experiment using a JPEG decoder example demonstrates an improvement in cosimulation speed over traditional HDL-based cosimulation. View full abstract»

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  • [Breaker page]

    Page(s): 77 - 78
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  • A software test program generator for verifying system-on-chips

    Page(s): 79 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios. View full abstract»

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  • Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model

    Page(s): 87 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    Verifying if an integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the nondeterministic extended finite state machine (NEFSM), and then propose an automatic stimulus generation approach based on the NEFSM. This approach is capable of providing numerous biasing options. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme. View full abstract»

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  • DVGen: a test generator for the transmeta Efficeon VLIW processor

    Page(s): 94 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    This paper describes DVGen, a tool that significantly improves the productivity of the verification engineer by facilitating the generation of self-checking tests from high-level specifications of test intent. DVGen automates resource management, instruction scheduling and computation of self-check reference values, allowing the engineer to focus on test intent through minimally-constrained specifications. It provides the control afforded by writing tests in assembly language as well as the power and flexibility afforded by writing tests in a high-level language. This paper details the scheduling of instructions and the methods of controlling code generation. The power of DVGen's interface with the architectural reference simulator is explored. Techniques employed by DVGen to perturb test generation in order to increase coverage from existing test specifications are presented. Following that, the ability of DVGen to combine diverse specifications intelligently in order to create tests that setup and trigger concurrent interesting events is discussed. The paper concludes with a high-level discussion of DVGen's most salient features. View full abstract»

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  • [Breaker page]

    Page(s): 102 - 104
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  • Reuse in system-level stimuli-generation

    Page(s): 105 - 111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models. The paper describes our modeling framework, where systems are modeled mainly by declarative constructs with some procedural code. Separate test specifications are used to direct stimuli generation, but are not studied in this paper. We find that a high level of white-box reuse reduces costs and allows starting the verification process early. This result reflects gradual evolution of the systems we study and the effectiveness of the declarative modeling scheme. We discuss the possible influence of libraries of system-level constructs on reuse in languages such 'e' Vera, and SystemVerilog. View full abstract»

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  • Harnessing machine learning to improve the success rate of stimuli generation

    Page(s): 112 - 118
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    The initial state of a design under verification has a major impact on the ability of stimuli generators to successfully generate the requested stimuli. For complexity reasons, most stimuli generators use sequential solutions without planning ahead. Therefore, in many cases they fail to produce consistent stimuli due to an inadequate selection of the initial state. We propose a method, based on machine learning techniques, to improve generation success by learning the relationship between the initial state vector and generation success. We applied the proposed method in two different settings, with the objective of improving generation success and coverage in processor and system level generation. In both settings, the proposed method significantly reduced generation failures and enabled faster coverage. View full abstract»

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  • [Breaker page]

    Page(s): 119 - 120
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