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Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.

Date Nov. 30 2005-Dec. 2 2005

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  • Tenth Annual IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No. 05TH8856)

    Publication Year: 2005
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  • Copyright page

    Publication Year: 2005, Page(s): ii
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  • Chairs' welcome message

    Publication Year: 2005, Page(s): iii
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  • Committees

    Publication Year: 2005, Page(s): iv
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  • Table of contents

    Publication Year: 2005, Page(s):v - viii
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  • [Breaker page]

    Publication Year: 2005, Page(s):1 - 2
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  • Simulation-based functional test generation for embedded processors

    Publication Year: 2005, Page(s):3 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key to develop a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the growth in design size. This work proposes a functiona... View full abstract»

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  • Scalable defect mapping and configuration of memory-based nanofabrics

    Publication Year: 2005, Page(s):11 - 18
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The idea is to start by obtaining a defect map of the target nanofabric, and then configure the desired functionality 'around' its defective components. In this paper,... View full abstract»

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  • Improvement of fault injection techniques based on VHDL code modification

    Publication Year: 2005, Page(s):19 - 26
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB) | HTML iconHTML

    Fault injection techniques based on the use of VHDL as design language offer important advantages with regard to other fault injection techniques. First, as they can be applied during the design phase of the system, they allow reducing the time-to-market. Second, this type of techniques presents high controllability and reachability. Among the different techniques, those based on the use of sabote... View full abstract»

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  • MVP: a mutation-based validation paradigm

    Publication Year: 2005, Page(s):27 - 34
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    A mutation-based validation paradigm that can handle complete high-level microprocessor implementations is presented. First, a control-based coverage measure is presented that is aimed at exposing design errors that incorrectly set control signal values. A method of automatically generating a complete set of modeled errors from this coverage metric is presented such that the instantiated modeled e... View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):35 - 36
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  • Establishing latch correspondence for embedded circuits of PowerPC microprocessors

    Publication Year: 2005, Page(s):37 - 44
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    We present a latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondenc... View full abstract»

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  • Sequential equivalence checking based on k-th invariants and circuit SAT solving

    Publication Year: 2005, Page(s):45 - 51
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (146 KB) | HTML iconHTML

    In this paper, we first present the concept of the k-th invariant. In contrast to the traditional invariants that hold for all cycles, k-th invariants guarantee to hold only after the k-th cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to comp... View full abstract»

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  • VERISEC: verifying equivalence of sequential circuits using SAT

    Publication Year: 2005, Page(s):52 - 59
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB) | HTML iconHTML

    In this paper we propose a framework to verify equivalence of sequential circuits using Boolean satisfiability (SAT). We tackle a problem that is harder than the traditional sequential hardware equivalence; specifically, we address the uninvestigated problem of verifying delay replaceability as stated in V. Singhal et al. (2001) of two sequential designs. This notion of sequential equivalence does... View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):60 - 62
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  • Automated clock inference for stream function-based system level specifications

    Publication Year: 2005, Page(s):63 - 70
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    Among system-level design frameworks and languages, system modeling approaches based on functional programming aim at rapid specification and prototyping of processing of data streams. Models constructed with functional programs provide highly modular and computationally correct models for prototyping and simulation purposes. For design space exploration, the functional programming frameworks prov... View full abstract»

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  • Cosimulation of ITRON-based embedded software with SystemC

    Publication Year: 2005, Page(s):71 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    This paper presents an RTOS-centric timed cosimulation with SystemC for embedded system design. In our cosimulation environment, a SystemC simulator and an RTOS kernel model are communicated and synchronized with each other. Our experiment using a JPEG decoder example demonstrates an improvement in cosimulation speed over traditional HDL-based cosimulation. View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):77 - 78
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  • A software test program generator for verifying system-on-chips

    Publication Year: 2005, Page(s):79 - 86
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences ... View full abstract»

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  • Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model

    Publication Year: 2005, Page(s):87 - 93
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Verifying if an integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper, we model the interface p... View full abstract»

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  • DVGen: a test generator for the transmeta Efficeon VLIW processor

    Publication Year: 2005, Page(s):94 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB) | HTML iconHTML

    This paper describes DVGen, a tool that significantly improves the productivity of the verification engineer by facilitating the generation of self-checking tests from high-level specifications of test intent. DVGen automates resource management, instruction scheduling and computation of self-check reference values, allowing the engineer to focus on test intent through minimally-constrained specif... View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):102 - 104
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  • Reuse in system-level stimuli-generation

    Publication Year: 2005, Page(s):105 - 111
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models. The paper describes our modeling framework, where systems are modeled mainly by declarative constructs with some procedural code. Separate test specifications are used to direct stimuli generation, but ar... View full abstract»

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  • Harnessing machine learning to improve the success rate of stimuli generation

    Publication Year: 2005, Page(s):112 - 118
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB) | HTML iconHTML

    The initial state of a design under verification has a major impact on the ability of stimuli generators to successfully generate the requested stimuli. For complexity reasons, most stimuli generators use sequential solutions without planning ahead. Therefore, in many cases they fail to produce consistent stimuli due to an inadequate selection of the initial state. We propose a method, based on ma... View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):119 - 120
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